commit a6aec7e
Michael Forney
·
2013-07-01 04:28:13 +0000 UTC
parent aa380ec
Style
3 files changed,
+17,
-56
+2,
-1
1@@ -4,7 +4,8 @@
2 #include <stdio.h>
3 #include <xf86drm.h>
4
5-void intel_batch_initialize(struct intel_batch * batch, drm_intel_bufmgr * bufmgr)
6+void intel_batch_initialize(struct intel_batch * batch,
7+ drm_intel_bufmgr * bufmgr)
8 {
9 batch->bufmgr = bufmgr;
10 batch->command_count = 0;
+5,
-6
1@@ -5,7 +5,7 @@
2 #include <stdint.h>
3 #include <stdarg.h>
4
5-#include <libdrm/intel_bufmgr.h>
6+#include <intel_bufmgr.h>
7
8 #define INTEL_MAX_COMMANDS (1 << 13)
9
10@@ -14,7 +14,6 @@ struct intel_batch
11 drm_intel_bufmgr * bufmgr;
12 drm_intel_bo * bo;
13
14- //uint32_t header[13];
15 uint32_t commands[INTEL_MAX_COMMANDS];
16 uint32_t command_count;
17 };
18@@ -35,24 +34,24 @@ static inline uint32_t intel_batch_space(struct intel_batch * batch)
19
20
21 static inline void intel_batch_add_dword(struct intel_batch * batch,
22- uint32_t dword)
23+ uint32_t dword)
24 {
25 batch->commands[batch->command_count++] = dword;
26 }
27
28-static inline void intel_batch_add_dwords(struct intel_batch * batch, uint32_t count, ...)
29+static inline void intel_batch_add_dwords(struct intel_batch * batch,
30+ uint32_t count, ...)
31 {
32 va_list dwords;
33 va_start(dwords, count);
34 while (count--)
35- intel_batch_add_dword(batch, va_arg(dwords, int));
36+ intel_batch_add_dword(batch, va_arg(dwords, uint32_t));
37 va_end(dwords);
38 }
39
40 static inline uint32_t intel_batch_offset(struct intel_batch * batch,
41 uint32_t command_index)
42 {
43- //printf("intel_batch_offset(4): %u\n", (batch->command_count + command_index) << 2);
44 return (batch->command_count + command_index) << 2;
45 }
46
+10,
-49
1@@ -3,50 +3,13 @@
2
3 #include "batch.h"
4
5-#include <libdrm/i915_drm.h>
6+#include <i915_drm.h>
7
8 #define COMMAND_TYPE_2D 0x2
9
10 #define BLT_OPCODE_XY_COLOR_BLT 0x50
11 #define BLT_OPCODE_XY_SRC_COPY_BLT 0x53
12
13-#if 0
14-/* BR00 */
15-#define BLT_OP(opcode, dword_length) ( \
16- COMMAND_TYPE_2D << 29 /* 31:29 */ \
17- | opcode << 23 /* 28:23 */ \
18- | dword_length /* 7:0 */ \
19-)
20-
21-#define BR00_32BPP_WRITE_ALPHA (1 << 21) /* 21 */
22-#define BR00_32BPP_WRITE_RGB (1 << 20) /* 20 */
23-#define BR00_SRC_TILING_ENABLE (1 << 15) /* 15 */
24-#define BR00_DST_TILING_ENABLE (1 << 11) /* 11 */
25-
26-#define BLT_ADDRESS(address) (address)
27-#define BLT_COORD(x, y) (y << 16 | x)
28-
29-#define BR09(address) BLT_ADDRESS(address)
30-#define BR11(source_pitch) (source_pitch)
31-#define BR12(address) BLT_ADDRESS(address)
32-
33-/* BR13 */
34-#define BR13_COLOR_DEPTH(depth) (depth << 24) /* 25:24 */
35-#define BR13_COLOR_DEPTH_8BIT BR13_COLOR_DEPTH(0x0)
36-#define BR13_COLOR_DEPTH_16BIT_565 BR13_COLOR_DEPTH(0x1)
37-#define BR13_COLOR_DEPTH_16BIT_1555 BR13_COLOR_DEPTH(0x2)
38-#define BR13_COLOR_DEPTH_32BIT BR13_COLOR_DEPTH(0x3)
39-
40-#define BR13_RASTER_OPERATION(op) (op << 16) /* 23:16 */
41-#define BR13_RASTER_OPERATION_SOURCE BR13_RASTER_OPERATION(0xcc)
42-#define BR13_RASTER_OPERATION_PATTERN BR13_RASTER_OPERATION(0xf0)
43-
44-#define BR16(color) (color)
45-#define BR22(x, y) BLT_COORD(x, y)
46-#define BR23(x, y) BLT_COORD(x, y)
47-#define BR26(x, y) BLT_COORD(x, y)
48-#endif
49-
50 #define BR00_32BPP_BYTE_MASK_ALPHA (1 << 0)
51 #define BR00_32BPP_BYTE_MASK_COLOR (1 << 1)
52
53@@ -151,12 +114,12 @@ static inline void xy_src_copy_blt(struct intel_batch * batch,
54 drm_intel_bo_get_tiling(dst, &dst_tiling_mode, &swizzle);
55 drm_intel_bo_get_tiling(src, &src_tiling_mode, &swizzle);
56
57- //printf("src_tiling: %u, dst_tiling: %u\n", src_tiling_mode, dst_tiling_mode);
58-
59- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
60- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
61- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 7), src, 0,
62- I915_GEM_DOMAIN_RENDER, 0);
63+ drm_intel_bo_emit_reloc_fence
64+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
65+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
66+ drm_intel_bo_emit_reloc_fence
67+ (batch->bo, intel_batch_offset(batch, 7), src, 0,
68+ I915_GEM_DOMAIN_RENDER, 0);
69
70 intel_batch_add_dwords(batch, 8,
71 br00(COMMAND_TYPE_2D, BLT_OPCODE_XY_SRC_COPY_BLT,
72@@ -186,11 +149,9 @@ static inline void xy_color_blt(struct intel_batch * batch,
73
74 drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
75
76- //printf("tiling: %u, swizzle: %u\n", tiling_mode, swizzle_mode);
77- //printf("pitch: %u\n", dst_pitch);
78-
79- drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
80- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
81+ drm_intel_bo_emit_reloc_fence
82+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
83+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
84
85 intel_batch_add_dwords(batch, 6,
86 br00(COMMAND_TYPE_2D, BLT_OPCODE_XY_COLOR_BLT,