commit cfc3346
Michael Forney
·
2013-06-14 09:52:35 +0000 UTC
parent 27f27f1
Use intel_bufmgr for buffer management
+2,
-1
1@@ -27,7 +27,8 @@ libswc_la_SOURCES = \
2 egl.c egl.h
3
4 libswc_la_LIBADD = $(wayland_server_LIBS) $(udev_LIBS) $(xkbcommon_LIBS) \
5- $(drm_LIBS) $(gbm_LIBS) $(egl_LIBS) $(pixman_LIBS) intel/libintel.la
6+ $(drm_LIBS) $(drm_intel_LIBS) $(gbm_LIBS) $(egl_LIBS) $(pixman_LIBS) \
7+ intel/libintel.la
8
9 # testclient_SOURCES = \
10 # testclient.c
M
buffer.c
+8,
-62
1@@ -6,41 +6,23 @@
2 #include <xf86drm.h>
3 #include <xf86drmMode.h>
4
5-/* Returns the next multiple of the eth power of 2 */
6-static inline uint32_t next_multiple_power_2(uint32_t n, uint32_t e)
7-{
8- return (n + (1 << e) - 1) & ~((1 << e) - 1);
9-}
10-
11-static void destroy_image(pixman_image_t * image, void * data)
12-{
13- struct swc_buffer * buffer = data;
14-
15- munmap(pixman_image_get_data(image), buffer->bo.size);
16-}
17-
18 bool swc_buffer_initialize(struct swc_buffer * buffer, struct swc_drm * drm,
19 uint32_t width, uint32_t height)
20 {
21 uint32_t size;
22-
23- buffer->image = NULL;
24+ uint32_t tiling_mode = I915_TILING_X;
25+ unsigned long pitch;
26
27 buffer->width = width;
28 buffer->height = height;
29
30- /* Round width up to next multiple of 512 */
31- buffer->pitch = next_multiple_power_2(width * 4, 9);
32-
33- /* Round height up to next multiple of 4 */
34- size = buffer->pitch * next_multiple_power_2(height, 2);
35+ buffer->bo = drm_intel_bo_alloc_tiled(drm->bufmgr, "fb", width, height, 4,
36+ &tiling_mode, &pitch, 0);
37
38- printf("width: %u, height: %u, pitch: %u, size: %u\n", width, height, buffer->pitch, size);
39-
40- intel_bo_initialize(drm->fd, &buffer->bo, size);
41+ buffer->pitch = pitch;
42
43 if (drmModeAddFB(drm->fd, width, height, 24, 32, buffer->pitch,
44- buffer->bo.handle, &buffer->id) != 0)
45+ buffer->bo->handle, &buffer->id) != 0)
46 {
47 printf("could not create FB from buffer handle\n");
48 goto error_buffer;
49@@ -49,10 +31,7 @@ bool swc_buffer_initialize(struct swc_buffer * buffer, struct swc_drm * drm,
50 return true;
51
52 error_buffer:
53- {
54- struct drm_gem_close close_arg = { .handle = buffer->bo.handle };
55- drmIoctl(drm->fd, DRM_IOCTL_GEM_CLOSE, &close_arg);
56- }
57+ drm_intel_bo_unreference(buffer->bo);
58 error_base:
59 return false;
60 }
61@@ -60,39 +39,6 @@ bool swc_buffer_initialize(struct swc_buffer * buffer, struct swc_drm * drm,
62 void swc_buffer_finish(struct swc_buffer * buffer, struct swc_drm * drm)
63 {
64 drmModeRmFB(drm->fd, buffer->id);
65- intel_bo_finalize(drm->fd, &buffer->bo);
66-}
67-
68-void swc_buffer_ref_image(struct swc_buffer * buffer, struct swc_drm * drm)
69-{
70- if (!buffer->image)
71- {
72- uint32_t * data;
73- struct drm_i915_gem_mmap mmap_arg = {
74- .handle = buffer->bo.handle,
75- .size = buffer->bo.size
76- };
77-
78- if (drmCommandWriteRead(drm->fd, DRM_I915_GEM_MMAP, &mmap_arg,
79- sizeof mmap_arg) != 0)
80- {
81- printf("could not mmap buffer\n");
82- return;
83- }
84-
85- data = (void *) mmap_arg.addr_ptr;
86- buffer->image = pixman_image_create_bits(PIXMAN_x8r8g8b8,
87- buffer->width, buffer->height,
88- data, buffer->pitch);
89- pixman_image_set_destroy_function(buffer->image, &destroy_image, buffer);
90- }
91- else
92- pixman_image_ref(buffer->image);
93-}
94-
95-void swc_buffer_unref_image(struct swc_buffer * buffer)
96-{
97- if (pixman_image_unref(buffer->image))
98- buffer->image = NULL;
99+ drm_intel_bo_unreference(buffer->bo);
100 }
101
M
buffer.h
+2,
-6
1@@ -2,7 +2,6 @@
2 #define SWC_BUFFER_H 1
3
4 #include "drm.h"
5-#include "intel/bo.h"
6
7 #include <stdbool.h>
8 #include <pixman.h>
9@@ -11,10 +10,7 @@ struct swc_buffer
10 {
11 uint32_t id;
12
13- struct intel_bo bo;
14-
15- /* Pixman image using the mapped buffer for use with SHM. */
16- pixman_image_t * image;
17+ drm_intel_bo * bo;
18
19 uint32_t width, height, pitch;
20 };
21@@ -24,7 +20,7 @@ bool swc_buffer_initialize(struct swc_buffer * buffer, struct swc_drm * drm,
22
23 void swc_buffer_finish(struct swc_buffer * buffer, struct swc_drm * drm);
24
25-void swc_buffer_ref_image(struct swc_buffer * buffer, struct swc_drm * drm);
26+void swc_buffer_ref_image(struct swc_buffer * buffer);
27
28 void swc_buffer_unref_image(struct swc_buffer * buffer);
29
+1,
-0
1@@ -24,6 +24,7 @@ PKG_CHECK_MODULES([wayland_server], [wayland-server])
2 PKG_CHECK_MODULES([udev], [libudev])
3 PKG_CHECK_MODULES([xkbcommon], [xkbcommon])
4 PKG_CHECK_MODULES([drm], [libdrm])
5+PKG_CHECK_MODULES([drm_intel], [libdrm_intel])
6 PKG_CHECK_MODULES([gbm], [gbm])
7 PKG_CHECK_MODULES([egl], [egl])
8 PKG_CHECK_MODULES([pixman], [pixman-1])
M
drm.c
+16,
-0
1@@ -7,12 +7,14 @@
2 #include <libdrm/drm.h>
3 #include <xf86drm.h>
4 #include <libdrm/i915_drm.h>
5+#include <libdrm/intel_bufmgr.h>
6 //#include <xf86drmMode.h>
7 #include <wayland-util.h>
8
9 #include "drm.h"
10 #include "output.h"
11 #include "event.h"
12+#include "intel/batch.h"
13
14 static struct udev_device * find_primary_drm_device(struct udev * udev,
15 const char * seat)
16@@ -213,10 +215,23 @@ bool swc_drm_initialize(struct swc_drm * drm, struct udev * udev,
17 printf("has blt: %u\n", ret);
18 }
19
20+ drm->bufmgr = drm_intel_bufmgr_gem_init(drm->fd, INTEL_MAX_COMMANDS << 2);
21+
22+ if (!drm->bufmgr)
23+ {
24+ printf("could not create bufmgr\n");
25+ goto error_fd;
26+ }
27+
28+ //drm_intel_bufmgr_set_debug(drm->bufmgr, true);
29+ drm_intel_bufmgr_gem_enable_fenced_relocs(drm->bufmgr);
30+
31 udev_device_unref(drm_device);
32
33 return true;
34
35+ error_fd:
36+ close(drm->fd);
37 error_device:
38 udev_device_unref(drm_device);
39 error_base:
40@@ -225,6 +240,7 @@ bool swc_drm_initialize(struct swc_drm * drm, struct udev * udev,
41
42 void swc_drm_finish(struct swc_drm * drm)
43 {
44+ drm_intel_bufmgr_destroy(drm->bufmgr);
45 close(drm->fd);
46 }
47
M
drm.h
+3,
-0
1@@ -6,6 +6,7 @@
2 #include <libudev.h>
3 #include <gbm.h>
4 #include <wayland-server.h>
5+#include <libdrm/intel_bufmgr.h>
6
7 enum swc_drm_event
8 {
9@@ -17,6 +18,8 @@ struct swc_drm
10 int fd;
11 uint32_t id;
12
13+ drm_intel_bufmgr * bufmgr;
14+
15 uint32_t taken_output_ids;
16
17 struct wl_event_source * source;
+21,
-106
1@@ -5,130 +5,45 @@
2 #include <stdio.h>
3 #include <xf86drm.h>
4
5-void intel_batch_initialize(struct intel_batch * batch, int drm)
6+void intel_batch_initialize(struct intel_batch * batch, drm_intel_bufmgr * bufmgr)
7 {
8- batch->relocation_count = 0;
9- batch->exec_object_count = 0;
10+ batch->bufmgr = bufmgr;
11 batch->command_count = 0;
12- batch->drm = drm;
13+
14+ /* Alignment (4096) is not used */
15+ batch->bo = drm_intel_bo_alloc(bufmgr, "batchbuffer",
16+ sizeof batch->commands, 4096);
17+}
18+
19+void intel_batch_finalize(struct intel_batch * batch)
20+{
21+ drm_intel_bo_unreference(batch->bo);
22 }
23
24 void intel_batch_flush(struct intel_batch * batch)
25 {
26- struct intel_bo bo;
27- uint32_t index = batch->exec_object_count++;
28+ if (batch->command_count == 0)
29+ return;
30
31- mi_batch_buffer_end(batch);
32+ intel_batch_add_dword(batch, MI_BATCH_BUFFER_END);
33
34 /* Pad the batch buffer to the next quad-word. */
35 if (batch->command_count & 1)
36- mi_noop(batch, false, 0);
37-
38- printf("command count: %u\n", batch->command_count);
39-
40- intel_bo_initialize(batch->drm, &bo, batch->command_count << 2);
41- intel_bo_write(batch->drm, &bo, 0, batch->commands, batch->command_count << 2);
42-
43- printf("adding exec object with handle: %u\n", bo.handle);
44-
45- /* Add command buffer */
46- batch->exec_objects[index] = (struct drm_i915_gem_exec_object2) {
47- .handle = bo.handle,
48- .relocation_count = batch->relocation_count,
49- .relocs_ptr = (uint64_t) batch->relocations
50- };
51-
52- {
53- int ret;
54- struct drm_i915_gem_execbuffer2 execbuffer_arg = {
55- .buffers_ptr = (uint64_t) batch->exec_objects,
56- .buffer_count = batch->exec_object_count,
57- .batch_start_offset = 0, /* XXX: ? */
58- .batch_len = batch->command_count << 2,
59- .flags = I915_EXEC_RENDER
60- };
61+ intel_batch_add_dword(batch, MI_NOOP);
62
63- if ((ret = drmIoctl(batch->drm, DRM_IOCTL_I915_GEM_EXECBUFFER2,
64- &execbuffer_arg)) != 0)
65- {
66- printf("execbuffer failed: %u\n", -ret);
67- }
68- }
69-
70- intel_bo_finalize(batch->drm, &bo);
71-
72- /* Set offsets for all our execution objects (except the last one, our
73- * command object). */
74- for (index = 0; index < batch->exec_object_count - 1; ++index)
75- *batch->offsets[index] = batch->exec_objects[index].offset;
76+ drm_intel_bo_subdata(batch->bo, 0, batch->command_count << 2,
77+ batch->commands);
78+ int ret = drm_intel_bo_exec(batch->bo, batch->command_count << 2, NULL, 0,
79+ 0);
80+ //printf("ret: %d\n", ret);
81+ drm_intel_gem_bo_clear_relocs(batch->bo, 0);
82
83 batch->command_count = 0;
84- batch->relocation_count = 0;
85- batch->exec_object_count = 0;
86 }
87
88-#if 0
89-uint32_t * intel_batch_alloc(struct intel_batch * batch, uint32_t size)
90-{
91- uint32_t * commands;
92-
93- if (intel_batch_space(batch) < size)
94- intel_batch_flush(batch);
95-
96- commands = &batch->commands[batch->size];
97- batch->command_count += command_count;
98-
99- return commands;
100-}
101-#endif
102-
103 void intel_batch_ensure_space(struct intel_batch * batch, uint32_t size)
104 {
105 if (intel_batch_space(batch) < size)
106 intel_batch_flush(batch);
107 }
108
109-uint32_t intel_batch_space(struct intel_batch * batch)
110-{
111- /* XXX: reserved space */
112- return I915_MAX_COMMANDS - batch->command_count;
113-}
114-
115-uint64_t intel_batch_add_relocation(struct intel_batch * batch,
116- uint32_t batch_offset, struct intel_bo * bo,
117- uint32_t read_domains, uint32_t write_domain)
118-{
119- uint32_t index = batch->relocation_count++;
120-
121- intel_batch_add_exec_object(batch, bo);
122-
123- printf("offset: %u\n", (batch->command_count + batch_offset) << 2);
124- printf("current: %u\n", *((uint32_t *)(((void *) batch->commands) + ((batch->command_count + batch_offset) << 2))));
125-
126- batch->relocations[index] = (struct drm_i915_gem_relocation_entry) {
127- .target_handle = bo->handle,
128- /* XXX: delta */
129- /* XXX: offset */
130- .offset = (batch->command_count + batch_offset) << 2,
131- .presumed_offset = bo->last_offset,
132- .read_domains = read_domains,
133- .write_domain = write_domain
134- };
135-
136- /* Return our offset guess */
137- return bo->last_offset;
138-}
139-
140-void intel_batch_add_exec_object(struct intel_batch * batch, struct intel_bo * bo)
141-{
142- uint32_t index = batch->exec_object_count++;
143-
144- printf("adding exec object with handle: %u\n", bo->handle);
145-
146- batch->exec_objects[index] = (struct drm_i915_gem_exec_object2) {
147- .handle = bo->handle
148- };
149-
150- batch->offsets[index] = &bo->last_offset;
151-}
152-
+20,
-20
1@@ -7,35 +7,34 @@
2 #include <stdint.h>
3 #include <stdarg.h>
4
5-#include <libdrm/i915_drm.h>
6+#include <libdrm/intel_bufmgr.h>
7
8-#define I915_MAX_COMMANDS (1 << 15)
9-#define I915_MAX_RELOCATIONS (1 << 11)
10-#define I915_MAX_EXEC_OBJECTS (1 << 11)
11+#define INTEL_MAX_COMMANDS (1 << 13)
12
13 struct intel_batch
14 {
15- int drm;
16-
17- struct drm_i915_gem_relocation_entry relocations[I915_MAX_RELOCATIONS];
18- uint64_t * offsets[I915_MAX_RELOCATIONS];
19- uint32_t relocation_count;
20-
21- struct drm_i915_gem_exec_object2 exec_objects[I915_MAX_EXEC_OBJECTS];
22- uint32_t exec_object_count;
23+ drm_intel_bufmgr * bufmgr;
24+ drm_intel_bo * bo;
25
26 //uint32_t header[13];
27- uint32_t commands[I915_MAX_COMMANDS];
28+ uint32_t commands[INTEL_MAX_COMMANDS];
29 uint32_t command_count;
30 };
31
32-void intel_batch_initialize(struct intel_batch * batch, int drm);
33+void intel_batch_initialize(struct intel_batch * batch, drm_intel_bufmgr * bufmgr);
34+
35+void intel_batch_finalize(struct intel_batch * batch);
36
37 void intel_batch_flush(struct intel_batch * batch);
38
39 void intel_batch_ensure_space(struct intel_batch * batch, uint32_t size);
40
41-uint32_t intel_batch_space(struct intel_batch * batch);
42+static inline uint32_t intel_batch_space(struct intel_batch * batch)
43+{
44+ /* XXX: reserved space */
45+ return INTEL_MAX_COMMANDS - batch->command_count;
46+}
47+
48
49 static inline void intel_batch_add_dword(struct intel_batch * batch,
50 uint32_t dword)
51@@ -52,11 +51,12 @@ static inline void intel_batch_add_dwords(struct intel_batch * batch, uint32_t c
52 va_end(dwords);
53 }
54
55-uint64_t intel_batch_add_relocation(struct intel_batch * batch,
56- uint32_t batch_offset, struct intel_bo * bo,
57- uint32_t read_domains, uint32_t write_domain);
58-
59-void intel_batch_add_exec_object(struct intel_batch * batch, struct intel_bo * bo);
60+static inline uint32_t intel_batch_offset(struct intel_batch * batch,
61+ uint32_t command_index)
62+{
63+ //printf("intel_batch_offset(4): %u\n", (batch->command_count + command_index) << 2);
64+ return (batch->command_count + command_index) << 2;
65+}
66
67 #endif
68
+81,
-52
1@@ -1,16 +1,54 @@
2 #ifndef SWC_I915_BLT_H
3 #define SWC_I915_BLT_H 1
4
5-#include "intel/bo.h"
6-#include "intel/batch.h"
7+#include "batch.h"
8
9-#define BR00_CLIENT_2D 0x2
10+#include <libdrm/i915_drm.h>
11
12-#define BR00_OPCODE_XY_COLOR_BLT 0x50
13-#define BR00_OPCODE_XY_SRC_COPY_BLT 0x53
14+#define COMMAND_TYPE_2D 0x2
15
16-#define BR00_32BPP_BYTE_MASK_ALPHA (1 << 1)
17-#define BR00_32BPP_BYTE_MASK_COLOR (1 << 2)
18+#define BLT_OPCODE_XY_COLOR_BLT 0x50
19+#define BLT_OPCODE_XY_SRC_COPY_BLT 0x53
20+
21+#if 0
22+/* BR00 */
23+#define BLT_OP(opcode, dword_length) ( \
24+ COMMAND_TYPE_2D << 29 /* 31:29 */ \
25+ | opcode << 23 /* 28:23 */ \
26+ | dword_length /* 7:0 */ \
27+)
28+
29+#define BR00_32BPP_WRITE_ALPHA (1 << 21) /* 21 */
30+#define BR00_32BPP_WRITE_RGB (1 << 20) /* 20 */
31+#define BR00_SRC_TILING_ENABLE (1 << 15) /* 15 */
32+#define BR00_DST_TILING_ENABLE (1 << 11) /* 11 */
33+
34+#define BLT_ADDRESS(address) (address)
35+#define BLT_COORD(x, y) (y << 16 | x)
36+
37+#define BR09(address) BLT_ADDRESS(address)
38+#define BR11(source_pitch) (source_pitch)
39+#define BR12(address) BLT_ADDRESS(address)
40+
41+/* BR13 */
42+#define BR13_COLOR_DEPTH(depth) (depth << 24) /* 25:24 */
43+#define BR13_COLOR_DEPTH_8BIT BR13_COLOR_DEPTH(0x0)
44+#define BR13_COLOR_DEPTH_16BIT_565 BR13_COLOR_DEPTH(0x1)
45+#define BR13_COLOR_DEPTH_16BIT_1555 BR13_COLOR_DEPTH(0x2)
46+#define BR13_COLOR_DEPTH_32BIT BR13_COLOR_DEPTH(0x3)
47+
48+#define BR13_RASTER_OPERATION(op) (op << 16) /* 23:16 */
49+#define BR13_RASTER_OPERATION_SOURCE BR13_RASTER_OPERATION(0xcc)
50+#define BR13_RASTER_OPERATION_PATTERN BR13_RASTER_OPERATION(0xf0)
51+
52+#define BR16(color) (color)
53+#define BR22(x, y) BLT_COORD(x, y)
54+#define BR23(x, y) BLT_COORD(x, y)
55+#define BR26(x, y) BLT_COORD(x, y)
56+#endif
57+
58+#define BR00_32BPP_BYTE_MASK_ALPHA (1 << 0)
59+#define BR00_32BPP_BYTE_MASK_COLOR (1 << 1)
60
61 static inline uint32_t br00(uint8_t client, uint8_t opcode,
62 uint8_t mask_32bpp,
63@@ -100,78 +138,69 @@ static inline uint32_t br26(uint16_t source_y1, uint16_t source_x1)
64 };
65
66 static inline void xy_src_copy_blt(struct intel_batch * batch,
67- struct intel_bo * src, uint16_t src_pitch,
68+ drm_intel_bo * src, uint16_t src_pitch,
69 uint16_t src_x, uint16_t src_y,
70- struct intel_bo * dst, uint16_t dst_pitch,
71+ drm_intel_bo * dst, uint16_t dst_pitch,
72 uint16_t dst_x, uint16_t dst_y,
73 uint16_t width, uint16_t height)
74 {
75-#if 0
76- intel_batch_add_dword(batch,
77- uint32_t * commands = intel_batch_alloc(batch, 8);
78- commands = (uint32_t *)
79- *commands++ = br00(BR00_CLIENT_2D, BR00_OPCODE_XY_SRC_COPY_BLT,
80- BR00_32BPP_BYTE_MASK_ALPHA | BR00_32BPP_BYTE_MASK_COLOR,
81- false, false, 6);
82- *commands++ = br13(false, BR13_COLOR_DEPTH_32BIT,
83- BR13_RASTER_OPERATION_SRC,
84- dst_pitch);
85- *commands++ = br22(dst_y, dst_x);
86- *commands++ = br23(dst_y + height, dst_x + width);
87- *commands++ = br09(0); /* XXX: dst address */
88- *commands++ = br26(src_y, src_x);
89- *commands++ = br11(src_pitch);
90- *commands++ = br12(0); /* XXX: src address */
91-#endif
92-
93- uint32_t dst_address, src_address;
94+ uint32_t src_tiling_mode, dst_tiling_mode, swizzle;
95
96 intel_batch_ensure_space(batch, 8);
97
98- dst_address = intel_batch_add_relocation(batch, 4, dst,
99- I915_GEM_DOMAIN_RENDER,
100- I915_GEM_DOMAIN_RENDER);
101- src_address = intel_batch_add_relocation(batch, 7, src,
102- I915_GEM_DOMAIN_RENDER, 0);
103+ drm_intel_bo_get_tiling(dst, &dst_tiling_mode, &swizzle);
104+ drm_intel_bo_get_tiling(src, &src_tiling_mode, &swizzle);
105+
106+ //printf("src_tiling: %u, dst_tiling: %u\n", src_tiling_mode, dst_tiling_mode);
107+
108+ drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
109+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
110+ drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 7), src, 0,
111+ I915_GEM_DOMAIN_RENDER, 0);
112
113 intel_batch_add_dwords(batch, 8,
114- br00(BR00_CLIENT_2D, BR00_OPCODE_XY_SRC_COPY_BLT,
115+ br00(COMMAND_TYPE_2D, BLT_OPCODE_XY_SRC_COPY_BLT,
116 BR00_32BPP_BYTE_MASK_ALPHA | BR00_32BPP_BYTE_MASK_COLOR,
117- false, false, 6),
118+ src_tiling_mode != I915_TILING_NONE,
119+ dst_tiling_mode != I915_TILING_NONE, 6),
120 br13(false, BR13_COLOR_DEPTH_32BIT, BR13_RASTER_OPERATION_SOURCE,
121- dst_pitch),
122+ dst_pitch >> 2),
123 br22(dst_y, dst_x),
124 br23(dst_y + height, dst_x + width),
125- br09(dst_address),
126+ br09(dst->offset),
127 br26(src_y, src_x),
128- br11(src_pitch),
129- br12(src_address)
130+ br11(src_pitch >> 2),
131+ br12(src->offset)
132 );
133 }
134
135 static inline void xy_color_blt(struct intel_batch * batch,
136- struct intel_bo * dst, uint16_t dst_pitch,
137- uint16_t dst_x, uint16_t dst_y,
138- uint16_t width, uint16_t height,
139+ drm_intel_bo * dst, uint16_t dst_pitch,
140+ uint16_t dst_x1, uint16_t dst_y1,
141+ uint16_t dst_x2, uint16_t dst_y2,
142 uint32_t color)
143 {
144- uint32_t dst_address;
145+ uint32_t tiling_mode, swizzle_mode;
146
147 intel_batch_ensure_space(batch, 6);
148
149- dst_address = intel_batch_add_relocation(batch, 4, dst,
150- I915_GEM_DOMAIN_RENDER,
151- I915_GEM_DOMAIN_RENDER);
152+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
153+
154+ //printf("tiling: %u, swizzle: %u\n", tiling_mode, swizzle_mode);
155+ //printf("pitch: %u\n", dst_pitch);
156+
157+ drm_intel_bo_emit_reloc_fence(batch->bo, intel_batch_offset(batch, 4), dst, 0,
158+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
159
160 intel_batch_add_dwords(batch, 6,
161- br00(BR00_CLIENT_2D, BR00_OPCODE_XY_COLOR_BLT,
162+ br00(COMMAND_TYPE_2D, BLT_OPCODE_XY_COLOR_BLT,
163 BR00_32BPP_BYTE_MASK_ALPHA | BR00_32BPP_BYTE_MASK_COLOR,
164- false, false, 4),
165+ false, tiling_mode != I915_TILING_NONE, 4),
166 br13(false, BR13_COLOR_DEPTH_32BIT, BR13_RASTER_OPERATION_PATTERN,
167- dst_pitch),
168- br22(dst_y, dst_x),
169- br23(dst_y + height, dst_x + width),
170- br09(dst_address),
171+ dst_pitch >> 2),
172+ br22(dst_y1, dst_x1),
173+ br23(dst_y2, dst_x2),
174+ br09(dst->offset),
175 br16(color)
176 );
177 }
+19,
-84
1@@ -8,90 +8,25 @@
2
3 #define COMMAND_TYPE_MI 0x0
4
5-#define MI_OPCODE_NOOP 0x00
6-#define MI_OPCODE_FLUSH 0x04
7-#define MI_OPCODE_BATCH_BUFFER_END 0x0A
8-#define MI_OPCODE_FLUSH_DW 0x04
9-#define MI_OPCODE_BATCH_BUFFER_START 0x31
10-
11-static inline void mi_noop(struct intel_batch * batch,
12- bool identification_number_write_enable,
13- uint32_t identification_number)
14-{
15- intel_batch_add_dword(batch,
16- COMMAND_TYPE_MI << 29 /* 31:29 */
17- | MI_OPCODE_NOOP << 23 /* 28:23 */
18- | identification_number_write_enable << 22 /* 22 */
19- | identification_number << 0 /* 21:0 */
20- );
21-}
22-
23-static inline void mi_flush(struct intel_batch * batch,
24- bool protected_memory_enable,
25- bool indirect_state_pointers_disable,
26- bool generic_media_state_clear,
27- bool global_snapshot_count_reset,
28- bool render_cache_flush_inhibit,
29- bool state_cache_invalidate)
30-{
31- intel_batch_add_dword(batch,
32- COMMAND_TYPE_MI << 29 /* 31:29 */
33- | MI_OPCODE_FLUSH << 23 /* 28:23 */
34- /* 22:7 */
35- | protected_memory_enable << 6 /* 6 */
36- | indirect_state_pointers_disable << 5 /* 5 */
37- | generic_media_state_clear << 4 /* 4 */
38- | global_snapshot_count_reset << 3 /* 3 */
39- | render_cache_flush_inhibit << 2 /* 2 */
40- | state_cache_invalidate /* 1 */
41- /* 0 */
42- );
43-}
44-
45-static inline void mi_flush_dw(struct intel_batch * batch)
46-{
47- intel_batch_add_dwords(batch, 4,
48- COMMAND_TYPE_MI << 29
49- | MI_OPCODE_FLUSH_DW << 23
50- | 2
51- ,
52- 0,
53- 0,
54- 0
55- );
56-}
57-
58-static inline void mi_batch_buffer_end(struct intel_batch * batch)
59-{
60- /* XXX: semaphore data dword / semaphore address */
61- intel_batch_add_dword(batch,
62- COMMAND_TYPE_MI << 29 /* 31:29 */
63- | MI_OPCODE_BATCH_BUFFER_END << 23 /* 28:23 */
64- /* 22:0 */
65- );
66-}
67-
68-static inline void mi_batch_buffer_start(struct intel_batch * batch,
69- bool encrypted_memory_enable,
70- bool clear_command_buffer_enable,
71- bool buffer_non_secure,
72- uint32_t buffer_address)
73-{
74- intel_batch_ensure_space(batch, 2);
75-
76- intel_batch_add_dwords(batch, 2,
77- COMMAND_TYPE_MI << 29 /* 31:29 */
78- | MI_OPCODE_BATCH_BUFFER_START << 23 /* 28:23 */
79- /* 22:13 */
80- | encrypted_memory_enable << 12 /* 12 */
81- | clear_command_buffer_enable << 11 /* 11 */
82- /* 10:9 */
83- | buffer_non_secure << 8 /* 8 */
84- | 0 /* 7:0 */
85- ,
86- buffer_address
87- );
88-}
89+#define MI_OP(opcode) ( \
90+ COMMAND_TYPE_MI << 29 /* 31:29 */ \
91+ | opcode << 23 /* 28:23 */ \
92+)
93+
94+#define MI_NOOP MI_OP(0x00)
95+#define MI_FLUSH MI_OP(0x04)
96+#define MI_BATCH_BUFFER_END MI_OP(0x0A)
97+
98+/* MI_NOOP */
99+#define MI_NOOP_IDENTIFICATION_NUMBER(number) (1 << 22 | number)
100+
101+/* MI_FLUSH */
102+#define MI_FLUSH_ENABLE_PROTECTED_MEMORY (1 << 6)
103+#define MI_FLUSH_DISABLE_INDIRECT_STATE_POINTERS (1 << 5)
104+#define MI_FLUSH_CLEAR_GENERIC_MEDIA_STATE (1 << 3)
105+#define MI_FLUSH_RESET_GLOBAL_SNAPSHOT_COUNT (1 << 3)
106+#define MI_FLUSH_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
107+#define MI_FLUSH_INVALIDATE_STATE_INSTRUCTION_CACHE (1 << 2)
108
109 #endif
110
M
output.c
+2,
-2
1@@ -110,7 +110,7 @@ bool swc_output_initialize(struct swc_output * output, struct swc_drm * drm,
2 uint32_t line[output->width];
3 uint32_t x, y;
4 struct drm_i915_gem_pwrite arg = {
5- .handle = output->buffers[0].bo.handle,
6+ .handle = output->buffers[0].bo->handle,
7 .size = sizeof line,
8 .data_ptr = (uint64_t) line
9 };
10@@ -127,7 +127,7 @@ bool swc_output_initialize(struct swc_output * output, struct swc_drm * drm,
11 color = 0x00333399;
12
13 arg.offset = 0;
14- arg.handle = output->buffers[1].bo.handle;
15+ arg.handle = output->buffers[1].bo->handle;
16
17 for (x = 0; x < output->width; ++x)
18 line[x] = color;
+15,
-9
1@@ -66,11 +66,16 @@ static void repaint_surface_for_output(struct swc_renderer * renderer,
2
3 if (wl_buffer_is_shm(surface->state.buffer))
4 {
5+ pixman_image_t * buffer_image;
6+
7 printf("repainting shm surface\n");
8+ buffer_image = pixman_image_create_bits_no_clear
9+ (PIXMAN_x8r8g8b8, back_buffer->width, back_buffer->height,
10+ back_buffer->bo->virtual, back_buffer->pitch);
11+
12 pixman_image_composite32(PIXMAN_OP_SRC,
13 surface->renderer_state.shm.image, NULL,
14- back_buffer->image,
15- 0, 0, 0, 0, 0, 0,
16+ buffer_image, 0, 0, 0, 0, 0, 0,
17 surface->geometry.width,
18 surface->geometry.height);
19 }
20@@ -92,13 +97,14 @@ bool swc_renderer_initialize(struct swc_renderer * renderer,
21 {
22 renderer->drm = drm;
23
24- intel_batch_initialize(&renderer->batch, drm->fd);
25+ intel_batch_initialize(&renderer->batch, drm->bufmgr);
26
27 return true;
28 }
29
30 void swc_renderer_finalize(struct swc_renderer * renderer)
31 {
32+ intel_batch_finalize(&renderer->batch);
33 }
34
35 void swc_renderer_repaint_output(struct swc_renderer * renderer,
36@@ -117,7 +123,7 @@ void swc_renderer_repaint_output(struct swc_renderer * renderer,
37 }
38 }
39
40- xy_color_blt(&renderer->batch, &swc_output_get_back_buffer(output)->bo,
41+ xy_color_blt(&renderer->batch, swc_output_get_back_buffer(output)->bo,
42 swc_output_get_back_buffer(output)->pitch, 0, 0, 500, 500,
43 0xffffffff);
44
45@@ -147,8 +153,8 @@ void swc_renderer_attach(struct swc_renderer * renderer,
46 {
47 if (surface->output_mask & (1 << output->id))
48 {
49- swc_buffer_ref_image(&output->buffers[0], renderer->drm);
50- swc_buffer_ref_image(&output->buffers[1], renderer->drm);
51+ swc_buffer_ref_image(&output->buffers[0]);
52+ swc_buffer_ref_image(&output->buffers[1]);
53 }
54 }
55 }
56@@ -159,9 +165,9 @@ void swc_renderer_attach(struct swc_renderer * renderer,
57 struct intel_region * region = image->region;
58 drm_intel_bo * bo = region->bo;
59
60- surface->renderer_state.drm.bo = (struct intel_bo) {
61- .handle = bo->handle
62- };
63+ surface->renderer_state.drm.bo
64+ = drm_intel_bo_gem_create_from_name(renderer->drm->bufmgr,
65+ "surface", region->name);
66
67 surface->renderer_state.drm.pitch = region->pitch;
68
+2,
-2
1@@ -1,7 +1,7 @@
2 #ifndef SWC_SURFACE_STATE_H
3 #define SWC_SURFACE_STATE_H 1
4
5-#include "intel/bo.h"
6+#include <libdrm/intel_bufmgr.h>
7
8 #include <wayland-server.h>
9 #include <pixman.h>
10@@ -14,7 +14,7 @@ union swc_renderer_surface_state
11 } shm;
12 struct
13 {
14- struct intel_bo bo;
15+ drm_intel_bo * bo;
16 uint32_t pitch;
17 } drm;
18 };