commit 2b0441a
Michael Forney
·
2014-01-31 22:13:51 +0000 UTC
parent 573d91f
intel: Merge libintelbatch into wld
8 files changed,
+713,
-4
M
Makefile
+3,
-3
1@@ -34,8 +34,8 @@ ifeq ($(ENABLE_DRM),1)
2 WLD_HEADERS += drm.h
3
4 ifneq ($(findstring intel,$(DRM_DRIVERS)),)
5- WLD_REQUIRES_PRIVATE += libdrm_intel intelbatch
6- WLD_SOURCES += intel.c
7+ WLD_REQUIRES_PRIVATE += libdrm_intel
8+ WLD_SOURCES += intel.c intel/batch.c
9 WLD_CPPFLAGS += -DWITH_DRM_INTEL=1
10 endif
11
12@@ -110,7 +110,7 @@ pkgconfig = $(sort $(foreach pkg,$(1),$(if $($(pkg)_$(3)),$($(pkg)_$(3)), \
13 .PHONY: all
14 all: $(TARGETS)
15
16-include protocol/local.mk
17+include $(foreach dir,intel protocol,$(dir)/local.mk)
18
19 .deps:
20 @mkdir "$@"
M
intel.c
+2,
-1
1@@ -23,10 +23,11 @@
2
3 #include "drm-private.h"
4 #include "drm.h"
5+#include "intel/batch.h"
6+#include "intel/blt.h"
7 #include "wld-private.h"
8
9 #include <unistd.h>
10-#include <intelbatch.h>
11 #include <intel_bufmgr.h>
12 #include <i915_drm.h>
13
+107,
-0
1@@ -0,0 +1,107 @@
2+/* wld: intel/batch.c
3+ *
4+ * Copyright (c) 2013, 2014 Michael Forney
5+ *
6+ * Permission is hereby granted, free of charge, to any person obtaining a copy
7+ * of this software and associated documentation files (the "Software"), to deal
8+ * in the Software without restriction, including without limitation the rights
9+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10+ * copies of the Software, and to permit persons to whom the Software is
11+ * furnished to do so, subject to the following conditions:
12+ *
13+ * The above copyright notice and this permission notice shall be included in
14+ * all copies or substantial portions of the Software.
15+ *
16+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22+ * SOFTWARE.
23+ */
24+
25+#include "batch.h"
26+#include "mi.h"
27+
28+#include <i915_drm.h>
29+#include <stdlib.h>
30+
31+static const struct intel_device_info device_info_i965 = { .gen = 4 };
32+static const struct intel_device_info device_info_g4x = { .gen = 4 };
33+static const struct intel_device_info device_info_ilk = { .gen = 5 };
34+static const struct intel_device_info device_info_snb_gt1 = { .gen = 6 };
35+static const struct intel_device_info device_info_snb_gt2 = { .gen = 6 };
36+static const struct intel_device_info device_info_ivb_gt1 = { .gen = 7 };
37+static const struct intel_device_info device_info_ivb_gt2 = { .gen = 7 };
38+static const struct intel_device_info device_info_byt = { .gen = 7 };
39+static const struct intel_device_info device_info_hsw_gt1 = { .gen = 7 };
40+static const struct intel_device_info device_info_hsw_gt2 = { .gen = 7 };
41+static const struct intel_device_info device_info_hsw_gt3 = { .gen = 7 };
42+
43+static const struct intel_device_info * device_info(int device_id)
44+{
45+ switch (device_id)
46+ {
47+#define CHIPSET(device_id, type, name) \
48+ case device_id: return &device_info_ ## type;
49+#include "i965_pci_ids.h"
50+#undef CHIPSET
51+ default: return NULL;
52+ }
53+}
54+
55+struct intel_batch * intel_batch_new(drm_intel_bufmgr * bufmgr)
56+{
57+ struct intel_batch * batch;
58+ int device_id = drm_intel_bufmgr_gem_get_devid(bufmgr);
59+
60+ batch = malloc(sizeof *batch);
61+
62+ if (!batch)
63+ goto error0;
64+
65+ batch->command_count = 0;
66+ batch->device_info = device_info(device_id);
67+
68+ if (!batch->device_info)
69+ goto error1;
70+
71+ /* Alignment argument (4096) is not used */
72+ batch->bo = drm_intel_bo_alloc(bufmgr, "batchbuffer",
73+ sizeof batch->commands, 4096);
74+
75+ return batch;
76+
77+ error1:
78+ free(batch);
79+ error0:
80+ return NULL;
81+}
82+
83+void intel_batch_destroy(struct intel_batch * batch)
84+{
85+ drm_intel_bo_unreference(batch->bo);
86+ free(batch);
87+}
88+
89+void intel_batch_flush(struct intel_batch * batch)
90+{
91+ if (batch->command_count == 0)
92+ return;
93+
94+ intel_batch_add_dword(batch, MI_BATCH_BUFFER_END);
95+
96+ /* Pad the batch buffer to the next quad-word. */
97+ if (batch->command_count & 1)
98+ intel_batch_add_dword(batch, MI_NOOP);
99+
100+ drm_intel_bo_subdata(batch->bo, 0, batch->command_count << 2,
101+ batch->commands);
102+ drm_intel_bo_mrb_exec(batch->bo, batch->command_count << 2, NULL, 0, 0,
103+ batch->device_info->gen >= 6 ? I915_EXEC_BLT
104+ : I915_EXEC_DEFAULT);
105+ drm_intel_gem_bo_clear_relocs(batch->bo, 0);
106+ batch->command_count = 0;
107+}
108+
+102,
-0
1@@ -0,0 +1,102 @@
2+/* wld: intel/batch.h
3+ *
4+ * Copyright (c) 2013, 2014 Michael Forney
5+ *
6+ * Permission is hereby granted, free of charge, to any person obtaining a copy
7+ * of this software and associated documentation files (the "Software"), to deal
8+ * in the Software without restriction, including without limitation the rights
9+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10+ * copies of the Software, and to permit persons to whom the Software is
11+ * furnished to do so, subject to the following conditions:
12+ *
13+ * The above copyright notice and this permission notice shall be included in
14+ * all copies or substantial portions of the Software.
15+ *
16+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22+ * SOFTWARE.
23+ */
24+
25+#ifndef WLD_INTEL_BATCH_H
26+#define WLD_INTEL_BATCH_H
27+
28+#include <stdarg.h>
29+#include <stdint.h>
30+#include <intel_bufmgr.h>
31+
32+#define INTEL_BATCH_MAX_COMMANDS (1 << 13)
33+#define INTEL_BATCH_RESERVED_COMMANDS 2
34+#define INTEL_BATCH_SIZE (INTEL_BATCH_MAX_COMMANDS << 2)
35+
36+enum intel_batch_result
37+{
38+ INTEL_BATCH_SUCCESS,
39+ INTEL_BATCH_NO_SPACE
40+};
41+
42+struct intel_device_info
43+{
44+ int gen;
45+};
46+
47+struct intel_batch
48+{
49+ const struct intel_device_info * device_info;
50+ drm_intel_bo * bo;
51+ uint32_t commands[INTEL_BATCH_MAX_COMMANDS];
52+ uint32_t command_count;
53+};
54+
55+struct intel_batch * intel_batch_new(drm_intel_bufmgr * bufmgr);
56+
57+void intel_batch_destroy(struct intel_batch * batch);
58+
59+void intel_batch_flush(struct intel_batch * batch);
60+
61+static inline uint32_t intel_batch_check_space(struct intel_batch * batch,
62+ uint32_t size)
63+{
64+ return (INTEL_BATCH_MAX_COMMANDS - INTEL_BATCH_RESERVED_COMMANDS
65+ - batch->command_count) >= size;
66+}
67+
68+static inline void intel_batch_ensure_space(struct intel_batch * batch, uint32_t size)
69+{
70+ if (!intel_batch_check_space(batch, size))
71+ intel_batch_flush(batch);
72+}
73+
74+static inline void intel_batch_add_dword(struct intel_batch * batch,
75+ uint32_t dword)
76+{
77+ batch->commands[batch->command_count++] = dword;
78+}
79+
80+static inline void intel_batch_add_dwords_va(struct intel_batch * batch,
81+ uint32_t count, va_list dwords)
82+{
83+ while (count--)
84+ intel_batch_add_dword(batch, va_arg(dwords, uint32_t));
85+}
86+
87+static inline void intel_batch_add_dwords(struct intel_batch * batch,
88+ uint32_t count, ...)
89+{
90+ va_list dwords;
91+ va_start(dwords, count);
92+ intel_batch_add_dwords_va(batch, count, dwords);
93+ va_end(dwords);
94+}
95+
96+static inline uint32_t intel_batch_offset(struct intel_batch * batch,
97+ uint32_t command_index)
98+{
99+ return (batch->command_count + command_index) << 2;
100+}
101+
102+#endif
103+
+350,
-0
1@@ -0,0 +1,350 @@
2+/* wld: intel/blt.h
3+ *
4+ * Copyright (c) 2013, 2014 Michael Forney
5+ *
6+ * Permission is hereby granted, free of charge, to any person obtaining a copy
7+ * of this software and associated documentation files (the "Software"), to deal
8+ * in the Software without restriction, including without limitation the rights
9+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10+ * copies of the Software, and to permit persons to whom the Software is
11+ * furnished to do so, subject to the following conditions:
12+ *
13+ * The above copyright notice and this permission notice shall be included in
14+ * all copies or substantial portions of the Software.
15+ *
16+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22+ * SOFTWARE.
23+ */
24+
25+#ifndef WLD_INTEL_BLT_H
26+#define WLD_INTEL_BLT_H
27+
28+#include <i915_drm.h>
29+#include <intel_bufmgr.h>
30+
31+#define INTEL_CLIENT_BLT 0x2
32+
33+enum intel_blt_op
34+{
35+ INTEL_BLT_OP_XY_SETUP_BLT = 0x01,
36+ INTEL_BLT_OP_XY_TEXT_BLT = 0x26,
37+ INTEL_BLT_OP_XY_TEXT_IMMEDIATE_BLT = 0x31,
38+ INTEL_BLT_OP_XY_COLOR_BLT = 0x50,
39+ INTEL_BLT_OP_XY_SRC_COPY_BLT = 0x53
40+};
41+
42+enum intel_blt_32bpp_mask
43+{
44+ INTEL_BLT_32BPP_MASK_ALPHA = (1 << 0),
45+ INTEL_BLT_32BPP_MASK_RGB = (1 << 1)
46+};
47+
48+enum intel_blt_packing
49+{
50+ INTEL_BLT_PACKING_BIT = 0,
51+ INTEL_BLT_PACKING_BYTE = 1
52+};
53+
54+enum intel_blt_color_depth
55+{
56+ INTEL_BLT_COLOR_DEPTH_8BIT = 0x0,
57+ INTEL_BLT_COLOR_DEPTH_16BIT_565 = 0x1,
58+ INTEL_BLT_COLOR_DEPTH_16BIT_1555 = 0x2,
59+ INTEL_BLT_COLOR_DEPTH_32BIT = 0x3
60+};
61+
62+enum intel_blt_raster_operation
63+{
64+ INTEL_BLT_RASTER_OPERATION_SRC = 0xcc,
65+ INTEL_BLT_RASTER_OPERATION_PAT = 0xf0
66+};
67+
68+/* BR00 : BLT Opcode & Control */
69+#define INTEL_BLT_BR00_CLIENT(x) ((x) << 29) /* 31:29 */
70+#define INTEL_BLT_BR00_OP(x) ((x) << 22) /* 28:22 */
71+#define INTEL_BLT_BR00_32BPP_MASK(x) ((x) << 20) /* 21:20 */
72+ /* 19:17 */
73+#define INTEL_BLT_BR00_PACKING(x) ((x) << 16) /* 16 */
74+#define INTEL_BLT_BR00_SRC_TILING_ENABLE(x) ((x) << 15) /* 15 */
75+ /* 14:12 */
76+#define INTEL_BLT_BR00_DST_TILING_ENABLE(x) ((x) << 11) /* 11 */
77+#define INTEL_BLT_BR00_DWORD_LENGTH(x) ((x) << 0) /* 7:0 */
78+
79+/* BR01 : Setup BLT Raster OP, Control, and Destination Offset */
80+#define INTEL_BLT_BR01_SOLID_PATTERN(x) ((x) << 31) /* 31 */
81+#define INTEL_BLT_BR01_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
82+#define INTEL_BLT_BR01_MONO_SRC_TRANSPARENCY(x) ((x) << 29) /* 29 */
83+#define INTEL_BLT_BR01_MONO_PAT_TRANSPARENCY(x) ((x) << 28) /* 28 */
84+#define INTEL_BLT_BR01_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
85+#define INTEL_BLT_BR01_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
86+#define INTEL_BLT_BR01_DST_PITCH(x) ((x) << 0) /* 15:0 */
87+
88+/* BR05 : Setup Expansion Background Color */
89+#define INTEL_BLT_BR05_BACKGROUND_COLOR(x) ((x) << 0) /* 31:0 */
90+
91+/* BR06 : Setup Expansion Foreground Color */
92+#define INTEL_BLT_BR06_FOREGROUND_COLOR(x) ((x) << 0) /* 31:0 */
93+
94+/* BR07 : Setup Blit Color Pattern Address */
95+ /* 31:29 */
96+#define INTEL_BLT_BR07_PAT_ADDRESS(x) ((x) << 6) /* 28:6 */
97+ /* 5:0 */
98+
99+/* BR09 : Destination Address */
100+ /* 31:29 */
101+#define INTEL_BLT_BR09_DST_ADDRESS(x) ((x) << 0) /* 28:0 */
102+
103+/* BR11 : Source Pitch */
104+ /* 31:16 */
105+#define INTEL_BLT_BR11_SRC_PITCH(x) ((x) << 0) /* 15:0 */
106+
107+/* BR12 : Source Address */
108+ /* 31:29 */
109+#define INTEL_BLT_BR12_SRC_ADDRESS(x) ((x) << 0) /* 28:0 */
110+
111+/* BR13 : BLT Raster OP, Control, and Destination Pitch */
112+#define INTEL_BLT_BR13_SOLID_PATTERN(x) ((x) << 31) /* 31 */
113+#define INTEL_BLT_BR13_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
114+#define INTEL_BLT_BR13_MONO_SRC_TRANSPARENT(x) ((x) << 29) /* 29 */
115+#define INTEL_BLT_BR13_MONO_PAT_TRANSPARENT(x) ((x) << 28) /* 28 */
116+#define INTEL_BLT_BR13_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
117+#define INTEL_BLT_BR13_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
118+#define INTEL_BLT_BR13_DST_PITCH(x) ((x) << 0) /* 15:0 */
119+
120+/* BR16 : Pattern Expansion Background & Solid Pattern Color */
121+#define INTEL_BLT_BR16_COLOR(x) ((x) << 0) /* 31 : 0 */
122+
123+/* BR22 : Destination Top Left */
124+#define INTEL_BLT_BR22_DST_Y1(x) ((x) << 16) /* 31:16 */
125+#define INTEL_BLT_BR22_DST_X1(x) ((x) << 0) /* 16:0 */
126+
127+/* BR23 : Destination Bottom Right */
128+#define INTEL_BLT_BR23_DST_Y2(x) ((x) << 16) /* 31:16 */
129+#define INTEL_BLT_BR23_DST_X2(x) ((x) << 0) /* 16:0 */
130+
131+/* BR24 : Clip Rectangle Top Left */
132+ /* 31 */
133+#define INTEL_BLT_BR24_CLP_Y1(x) ((x) << 16) /* 30:16 */
134+ /* 15 */
135+#define INTEL_BLT_BR24_CLP_X1(x) ((x) << 0) /* 14:0 */
136+
137+/* BR25 : Clip Rectangle Bottom Right */
138+ /* 31 */
139+#define INTEL_BLT_BR25_CLP_Y2(x) ((x) << 16) /* 30:16 */
140+ /* 15 */
141+#define INTEL_BLT_BR25_CLP_X2(x) ((x) << 0) /* 14:0 */
142+
143+/* BR26 : Source Top Left */
144+#define INTEL_BLT_BR26_SRC_Y1(x) ((x) << 16) /* 31:16 */
145+#define INTEL_BLT_BR26_SRC_X1(x) ((x) << 0) /* 15:0 */
146+
147+static inline void xy_setup_blt(struct intel_batch * batch,
148+ bool monochrome_source_transparency,
149+ uint8_t raster_operation,
150+ uint32_t background_color,
151+ uint32_t foreground_color,
152+ drm_intel_bo * dst, uint16_t dst_pitch)
153+{
154+ uint32_t tiling_mode, swizzle_mode;
155+
156+ intel_batch_ensure_space(batch, 8);
157+
158+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
159+ drm_intel_bo_emit_reloc_fence
160+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
161+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
162+
163+ intel_batch_add_dwords(batch, 8,
164+ INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
165+ | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_SETUP_BLT)
166+ | INTEL_BLT_BR00_32BPP_MASK(INTEL_BLT_32BPP_MASK_ALPHA
167+ | INTEL_BLT_32BPP_MASK_RGB)
168+ | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
169+ | INTEL_BLT_BR00_DWORD_LENGTH(6),
170+
171+ INTEL_BLT_BR01_CLIPPING_ENABLE(false)
172+ | INTEL_BLT_BR01_MONO_SRC_TRANSPARENCY(monochrome_source_transparency)
173+ | INTEL_BLT_BR01_COLOR_DEPTH(INTEL_BLT_COLOR_DEPTH_32BIT)
174+ | INTEL_BLT_BR01_RASTER_OPERATION(raster_operation)
175+ | INTEL_BLT_BR01_DST_PITCH(tiling_mode == I915_TILING_NONE
176+ ? dst_pitch : dst_pitch >> 2),
177+
178+ /* XXX: No clipping yet */
179+ INTEL_BLT_BR24_CLP_Y1(0)
180+ | INTEL_BLT_BR24_CLP_X1(0),
181+
182+ INTEL_BLT_BR25_CLP_Y2(0)
183+ | INTEL_BLT_BR25_CLP_X2(0),
184+
185+ INTEL_BLT_BR09_DST_ADDRESS(dst->offset),
186+ INTEL_BLT_BR05_BACKGROUND_COLOR(background_color),
187+ INTEL_BLT_BR06_FOREGROUND_COLOR(foreground_color),
188+ INTEL_BLT_BR07_PAT_ADDRESS(0)
189+ );
190+}
191+
192+static inline int xy_text_blt(struct intel_batch * batch,
193+ drm_intel_bo * src, uint32_t src_offset,
194+ drm_intel_bo * dst,
195+ int16_t dst_x1, int16_t dst_y1,
196+ int16_t dst_x2, int16_t dst_y2)
197+{
198+ uint32_t tiling_mode, swizzle_mode;
199+
200+ if (!intel_batch_check_space(batch, 4))
201+ return INTEL_BATCH_NO_SPACE;
202+
203+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
204+
205+ drm_intel_bo_emit_reloc_fence
206+ (batch->bo, intel_batch_offset(batch, 3), src, src_offset,
207+ I915_GEM_DOMAIN_RENDER, 0);
208+
209+ intel_batch_add_dwords(batch, 4,
210+ INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
211+ | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_TEXT_BLT)
212+ | INTEL_BLT_BR00_PACKING(INTEL_BLT_PACKING_BYTE)
213+ | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
214+ | INTEL_BLT_BR00_DWORD_LENGTH(2),
215+
216+ INTEL_BLT_BR22_DST_Y1(dst_y1) | INTEL_BLT_BR22_DST_X1(dst_x1),
217+ INTEL_BLT_BR23_DST_Y2(dst_y2) | INTEL_BLT_BR23_DST_X2(dst_x2),
218+ INTEL_BLT_BR12_SRC_ADDRESS(src->offset + src_offset)
219+ );
220+
221+ return INTEL_BATCH_SUCCESS;
222+}
223+
224+static inline int xy_text_immediate_blt(struct intel_batch * batch,
225+ drm_intel_bo * dst,
226+ int16_t dst_x1, int16_t dst_y1,
227+ int16_t dst_x2, int16_t dst_y2,
228+ uint16_t count, uint32_t * immediates)
229+{
230+ /* Round up to the next even number. */
231+ uint8_t dwords = (count + 1) & ~1;
232+ uint32_t index;
233+ uint32_t tiling_mode, swizzle_mode;
234+
235+ if (!intel_batch_check_space(batch, 3 + dwords))
236+ return INTEL_BATCH_NO_SPACE;
237+
238+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
239+
240+ intel_batch_add_dwords(batch, 3,
241+ INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
242+ | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_TEXT_IMMEDIATE_BLT)
243+ | INTEL_BLT_BR00_PACKING(INTEL_BLT_PACKING_BYTE)
244+ | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
245+ | INTEL_BLT_BR00_DWORD_LENGTH(1 + dwords),
246+
247+ INTEL_BLT_BR22_DST_Y1(dst_y1) | INTEL_BLT_BR22_DST_X1(dst_x1),
248+ INTEL_BLT_BR23_DST_Y2(dst_y2) | INTEL_BLT_BR23_DST_X2(dst_x2)
249+ );
250+
251+ for (index = 0; index < count; ++index)
252+ intel_batch_add_dword(batch, *immediates++);
253+
254+ /* From BLT engine documentation:
255+ *
256+ * The IMMEDIATE_BLT data MUST transfer an even number of doublewords. The
257+ * BLT engine will hang if it does not get an even number of doublewords. */
258+ if (count & 1)
259+ intel_batch_add_dword(batch, 0);
260+
261+ return INTEL_BATCH_SUCCESS;
262+}
263+
264+static inline void xy_src_copy_blt(struct intel_batch * batch,
265+ drm_intel_bo * src, uint16_t src_pitch,
266+ uint16_t src_x, uint16_t src_y,
267+ drm_intel_bo * dst, uint16_t dst_pitch,
268+ uint16_t dst_x, uint16_t dst_y,
269+ uint16_t width, uint16_t height)
270+{
271+ uint32_t src_tiling_mode, dst_tiling_mode, swizzle;
272+
273+ intel_batch_ensure_space(batch, 8);
274+
275+ drm_intel_bo_get_tiling(dst, &dst_tiling_mode, &swizzle);
276+ drm_intel_bo_get_tiling(src, &src_tiling_mode, &swizzle);
277+
278+ drm_intel_bo_emit_reloc_fence
279+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
280+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
281+ drm_intel_bo_emit_reloc_fence
282+ (batch->bo, intel_batch_offset(batch, 7), src, 0,
283+ I915_GEM_DOMAIN_RENDER, 0);
284+
285+ intel_batch_add_dwords(batch, 8,
286+ INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
287+ | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_SRC_COPY_BLT)
288+ | INTEL_BLT_BR00_32BPP_MASK(INTEL_BLT_32BPP_MASK_ALPHA
289+ | INTEL_BLT_32BPP_MASK_RGB)
290+ | INTEL_BLT_BR00_SRC_TILING_ENABLE(src_tiling_mode != I915_TILING_NONE)
291+ | INTEL_BLT_BR00_DST_TILING_ENABLE(dst_tiling_mode != I915_TILING_NONE)
292+ | INTEL_BLT_BR00_DWORD_LENGTH(6),
293+
294+ INTEL_BLT_BR13_CLIPPING_ENABLE(false)
295+ | INTEL_BLT_BR13_COLOR_DEPTH(INTEL_BLT_COLOR_DEPTH_32BIT)
296+ | INTEL_BLT_BR13_RASTER_OPERATION(INTEL_BLT_RASTER_OPERATION_SRC)
297+ | INTEL_BLT_BR13_DST_PITCH(dst_tiling_mode == I915_TILING_NONE
298+ ? dst_pitch : dst_pitch >> 2),
299+
300+ INTEL_BLT_BR22_DST_Y1(dst_y) | INTEL_BLT_BR22_DST_X1(dst_x),
301+
302+ INTEL_BLT_BR23_DST_Y2(dst_y + height)
303+ | INTEL_BLT_BR23_DST_X2(dst_x + width),
304+
305+ INTEL_BLT_BR09_DST_ADDRESS(dst->offset),
306+ INTEL_BLT_BR26_SRC_Y1(src_y) | INTEL_BLT_BR26_SRC_X1(src_x),
307+ INTEL_BLT_BR11_SRC_PITCH(src_tiling_mode == I915_TILING_NONE
308+ ? src_pitch : src_pitch >> 2),
309+ INTEL_BLT_BR12_SRC_ADDRESS(src->offset)
310+ );
311+}
312+
313+static inline void xy_color_blt(struct intel_batch * batch,
314+ drm_intel_bo * dst, uint16_t dst_pitch,
315+ uint16_t dst_x1, uint16_t dst_y1,
316+ uint16_t dst_x2, uint16_t dst_y2,
317+ uint32_t color)
318+{
319+ uint32_t tiling_mode, swizzle_mode;
320+
321+ intel_batch_ensure_space(batch, 6);
322+
323+ drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
324+
325+ drm_intel_bo_emit_reloc_fence
326+ (batch->bo, intel_batch_offset(batch, 4), dst, 0,
327+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
328+
329+ intel_batch_add_dwords(batch, 6,
330+ INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
331+ | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_COLOR_BLT)
332+ | INTEL_BLT_BR00_32BPP_MASK(INTEL_BLT_32BPP_MASK_ALPHA
333+ | INTEL_BLT_32BPP_MASK_RGB)
334+ | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
335+ | INTEL_BLT_BR00_DWORD_LENGTH(4),
336+
337+ INTEL_BLT_BR13_CLIPPING_ENABLE(false)
338+ | INTEL_BLT_BR13_COLOR_DEPTH(INTEL_BLT_COLOR_DEPTH_32BIT)
339+ | INTEL_BLT_BR13_RASTER_OPERATION(INTEL_BLT_RASTER_OPERATION_PAT)
340+ | INTEL_BLT_BR13_DST_PITCH(tiling_mode == I915_TILING_NONE
341+ ? dst_pitch : dst_pitch >> 2),
342+
343+ INTEL_BLT_BR22_DST_Y1(dst_y1) | INTEL_BLT_BR22_DST_X1(dst_x1),
344+ INTEL_BLT_BR23_DST_Y2(dst_y2) | INTEL_BLT_BR23_DST_X2(dst_x2),
345+ INTEL_BLT_BR09_DST_ADDRESS(dst->offset),
346+ INTEL_BLT_BR16_COLOR(color)
347+ );
348+}
349+
350+#endif
351+
+93,
-0
1@@ -0,0 +1,93 @@
2+CHIPSET(0x29A2, i965, "Intel(R) 965G")
3+CHIPSET(0x2992, i965, "Intel(R) 965Q")
4+CHIPSET(0x2982, i965, "Intel(R) 965G")
5+CHIPSET(0x2972, i965, "Intel(R) 946GZ")
6+CHIPSET(0x2A02, i965, "Intel(R) 965GM")
7+CHIPSET(0x2A12, i965, "Intel(R) 965GME/GLE")
8+CHIPSET(0x2A42, g4x, "Mobile Intel® GM45 Express Chipset")
9+CHIPSET(0x2E02, g4x, "Intel(R) Integrated Graphics Device")
10+CHIPSET(0x2E12, g4x, "Intel(R) Q45/Q43")
11+CHIPSET(0x2E22, g4x, "Intel(R) G45/G43")
12+CHIPSET(0x2E32, g4x, "Intel(R) G41")
13+CHIPSET(0x2E42, g4x, "Intel(R) B43")
14+CHIPSET(0x2E92, g4x, "Intel(R) B43")
15+CHIPSET(0x0042, ilk, "Intel(R) Ironlake Desktop")
16+CHIPSET(0x0046, ilk, "Intel(R) Ironlake Mobile")
17+CHIPSET(0x0102, snb_gt1, "Intel(R) Sandybridge Desktop")
18+CHIPSET(0x0112, snb_gt2, "Intel(R) Sandybridge Desktop")
19+CHIPSET(0x0122, snb_gt2, "Intel(R) Sandybridge Desktop")
20+CHIPSET(0x0106, snb_gt1, "Intel(R) Sandybridge Mobile")
21+CHIPSET(0x0116, snb_gt2, "Intel(R) Sandybridge Mobile")
22+CHIPSET(0x0126, snb_gt2, "Intel(R) Sandybridge Mobile")
23+CHIPSET(0x010A, snb_gt1, "Intel(R) Sandybridge Server")
24+CHIPSET(0x0152, ivb_gt1, "Intel(R) Ivybridge Desktop")
25+CHIPSET(0x0162, ivb_gt2, "Intel(R) Ivybridge Desktop")
26+CHIPSET(0x0156, ivb_gt1, "Intel(R) Ivybridge Mobile")
27+CHIPSET(0x0166, ivb_gt2, "Intel(R) Ivybridge Mobile")
28+CHIPSET(0x015a, ivb_gt1, "Intel(R) Ivybridge Server")
29+CHIPSET(0x016a, ivb_gt2, "Intel(R) Ivybridge Server")
30+CHIPSET(0x0402, hsw_gt1, "Intel(R) Haswell Desktop")
31+CHIPSET(0x0412, hsw_gt2, "Intel(R) Haswell Desktop")
32+CHIPSET(0x0422, hsw_gt3, "Intel(R) Haswell Desktop")
33+CHIPSET(0x0406, hsw_gt1, "Intel(R) Haswell Mobile")
34+CHIPSET(0x0416, hsw_gt2, "Intel(R) Haswell Mobile")
35+CHIPSET(0x0426, hsw_gt3, "Intel(R) Haswell Mobile")
36+CHIPSET(0x040A, hsw_gt1, "Intel(R) Haswell Server")
37+CHIPSET(0x041A, hsw_gt2, "Intel(R) Haswell Server")
38+CHIPSET(0x042A, hsw_gt3, "Intel(R) Haswell Server")
39+CHIPSET(0x040B, hsw_gt1, "Intel(R) Haswell")
40+CHIPSET(0x041B, hsw_gt2, "Intel(R) Haswell")
41+CHIPSET(0x042B, hsw_gt3, "Intel(R) Haswell")
42+CHIPSET(0x040E, hsw_gt1, "Intel(R) Haswell")
43+CHIPSET(0x041E, hsw_gt2, "Intel(R) Haswell")
44+CHIPSET(0x042E, hsw_gt3, "Intel(R) Haswell")
45+CHIPSET(0x0C02, hsw_gt1, "Intel(R) Haswell Desktop")
46+CHIPSET(0x0C12, hsw_gt2, "Intel(R) Haswell Desktop")
47+CHIPSET(0x0C22, hsw_gt3, "Intel(R) Haswell Desktop")
48+CHIPSET(0x0C06, hsw_gt1, "Intel(R) Haswell Mobile")
49+CHIPSET(0x0C16, hsw_gt2, "Intel(R) Haswell Mobile")
50+CHIPSET(0x0C26, hsw_gt3, "Intel(R) Haswell Mobile")
51+CHIPSET(0x0C0A, hsw_gt1, "Intel(R) Haswell Server")
52+CHIPSET(0x0C1A, hsw_gt2, "Intel(R) Haswell Server")
53+CHIPSET(0x0C2A, hsw_gt3, "Intel(R) Haswell Server")
54+CHIPSET(0x0C0B, hsw_gt1, "Intel(R) Haswell")
55+CHIPSET(0x0C1B, hsw_gt2, "Intel(R) Haswell")
56+CHIPSET(0x0C2B, hsw_gt3, "Intel(R) Haswell")
57+CHIPSET(0x0C0E, hsw_gt1, "Intel(R) Haswell")
58+CHIPSET(0x0C1E, hsw_gt2, "Intel(R) Haswell")
59+CHIPSET(0x0C2E, hsw_gt3, "Intel(R) Haswell")
60+CHIPSET(0x0A02, hsw_gt1, "Intel(R) Haswell Desktop")
61+CHIPSET(0x0A12, hsw_gt2, "Intel(R) Haswell Desktop")
62+CHIPSET(0x0A22, hsw_gt3, "Intel(R) Haswell Desktop")
63+CHIPSET(0x0A06, hsw_gt1, "Intel(R) Haswell Mobile")
64+CHIPSET(0x0A16, hsw_gt2, "Intel(R) Haswell Mobile")
65+CHIPSET(0x0A26, hsw_gt3, "Intel(R) Haswell Mobile")
66+CHIPSET(0x0A0A, hsw_gt1, "Intel(R) Haswell Server")
67+CHIPSET(0x0A1A, hsw_gt2, "Intel(R) Haswell Server")
68+CHIPSET(0x0A2A, hsw_gt3, "Intel(R) Haswell Server")
69+CHIPSET(0x0A0B, hsw_gt1, "Intel(R) Haswell")
70+CHIPSET(0x0A1B, hsw_gt2, "Intel(R) Haswell")
71+CHIPSET(0x0A2B, hsw_gt3, "Intel(R) Haswell")
72+CHIPSET(0x0A0E, hsw_gt1, "Intel(R) Haswell")
73+CHIPSET(0x0A1E, hsw_gt2, "Intel(R) Haswell")
74+CHIPSET(0x0A2E, hsw_gt3, "Intel(R) Haswell")
75+CHIPSET(0x0D02, hsw_gt1, "Intel(R) Haswell Desktop")
76+CHIPSET(0x0D12, hsw_gt2, "Intel(R) Haswell Desktop")
77+CHIPSET(0x0D22, hsw_gt3, "Intel(R) Haswell Desktop")
78+CHIPSET(0x0D06, hsw_gt1, "Intel(R) Haswell Mobile")
79+CHIPSET(0x0D16, hsw_gt2, "Intel(R) Haswell Mobile")
80+CHIPSET(0x0D26, hsw_gt3, "Intel(R) Haswell Mobile")
81+CHIPSET(0x0D0A, hsw_gt1, "Intel(R) Haswell Server")
82+CHIPSET(0x0D1A, hsw_gt2, "Intel(R) Haswell Server")
83+CHIPSET(0x0D2A, hsw_gt3, "Intel(R) Haswell")
84+CHIPSET(0x0D0B, hsw_gt1, "Intel(R) Haswell")
85+CHIPSET(0x0D1B, hsw_gt2, "Intel(R) Haswell")
86+CHIPSET(0x0D2B, hsw_gt3, "Intel(R) Haswell")
87+CHIPSET(0x0D0E, hsw_gt1, "Intel(R) Haswell")
88+CHIPSET(0x0D1E, hsw_gt2, "Intel(R) Haswell")
89+CHIPSET(0x0D2E, hsw_gt3, "Intel(R) Haswell")
90+CHIPSET(0x0F31, byt, "Intel(R) Bay Trail")
91+CHIPSET(0x0F32, byt, "Intel(R) Bay Trail")
92+CHIPSET(0x0F33, byt, "Intel(R) Bay Trail")
93+CHIPSET(0x0157, byt, "Intel(R) Bay Trail")
94+CHIPSET(0x0155, byt, "Intel(R) Bay Trail")
+6,
-0
1@@ -0,0 +1,6 @@
2+# wld: intel/local.mk
3+
4+dir := intel
5+
6+include common.mk
7+
+50,
-0
1@@ -0,0 +1,50 @@
2+/* wld: intel/mi.h
3+ *
4+ * Copyright (c) 2013, 2014 Michael Forney
5+ *
6+ * Permission is hereby granted, free of charge, to any person obtaining a copy
7+ * of this software and associated documentation files (the "Software"), to deal
8+ * in the Software without restriction, including without limitation the rights
9+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10+ * copies of the Software, and to permit persons to whom the Software is
11+ * furnished to do so, subject to the following conditions:
12+ *
13+ * The above copyright notice and this permission notice shall be included in
14+ * all copies or substantial portions of the Software.
15+ *
16+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22+ * SOFTWARE.
23+ */
24+
25+#ifndef WLD_INTEL_MI_H
26+#define WLD_INTEL_MI_H
27+
28+#define INTEL_CLIENT_MI 0x0
29+
30+#define MI_OP(opcode) ( \
31+ INTEL_CLIENT_MI << 29 /* 31:29 */ \
32+ | opcode << 23 /* 28:23 */ \
33+)
34+
35+#define MI_NOOP MI_OP(0x00)
36+#define MI_FLUSH MI_OP(0x04)
37+#define MI_BATCH_BUFFER_END MI_OP(0x0A)
38+
39+/* MI_NOOP */
40+#define MI_NOOP_IDENTIFICATION_NUMBER(number) (1 << 22 | number)
41+
42+/* MI_FLUSH */
43+#define MI_FLUSH_ENABLE_PROTECTED_MEMORY (1 << 6)
44+#define MI_FLUSH_DISABLE_INDIRECT_STATE_POINTERS (1 << 5)
45+#define MI_FLUSH_CLEAR_GENERIC_MEDIA_STATE (1 << 4)
46+#define MI_FLUSH_RESET_GLOBAL_SNAPSHOT_COUNT (1 << 3)
47+#define MI_FLUSH_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
48+#define MI_FLUSH_INVALIDATE_STATE_INSTRUCTION_CACHE (1 << 1)
49+
50+#endif
51+