commit d455967
Devin J. Pohly
·
2017-10-31 02:04:49 +0000 UTC
parent 9f356a6
intel: implement Broadwell (gen8) support Worked from PRMs and did not have gen8 HW to test. Device IDs can be added to the header file to enable support once they are tested. Signed-off-by: Devin J. Pohly <djpohly@gmail.com>
1 files changed,
+70,
-29
+70,
-29
1@@ -90,12 +90,12 @@ enum blt_raster_operation
2 /* BR06 : Setup Expansion Foreground Color */
3 #define BLT_BR06_FOREGROUND_COLOR(x) ((x) << 0) /* 31:0 */
4
5-/* BR07 : Setup Blit Color Pattern Address */
6+/* BR07 : Setup Blit Color Pattern Address Low Bits */
7 /* 31:29 */
8 #define BLT_BR07_PAT_ADDRESS(x) ((x) << 6) /* 28:6 */
9 /* 5:0 */
10
11-/* BR09 : Destination Address */
12+/* BR09 : Destination Address Low Bits */
13 /* 31:29 */
14 #define BLT_BR09_DST_ADDRESS(x) ((x) << 0) /* 28:0 */
15
16@@ -103,7 +103,7 @@ enum blt_raster_operation
17 /* 31:16 */
18 #define BLT_BR11_SRC_PITCH(x) ((x) << 0) /* 15:0 */
19
20-/* BR12 : Source Address */
21+/* BR12 : Source Address Low Bits */
22 /* 31:29 */
23 #define BLT_BR12_SRC_ADDRESS(x) ((x) << 0) /* 28:0 */
24
25@@ -143,6 +143,18 @@ enum blt_raster_operation
26 #define BLT_BR26_SRC_Y1(x) ((x) << 16) /* 31:16 */
27 #define BLT_BR26_SRC_X1(x) ((x) << 0) /* 15:0 */
28
29+/* BR27 : Destination Address High Bits */
30+ /* 31:16 */
31+#define BLT_BR27_DST_ADDRESS_HI(x) ((x) << 0) /* 15:0 */
32+
33+/* BR28 : Source Address High Bits */
34+ /* 31:16 */
35+#define BLT_BR28_SRC_ADDRESS_HI(x) ((x) << 0) /* 15:0 */
36+
37+/* BR30 : Setup Blit Color Pattern Address High Bits */
38+ /* 31:16 */
39+#define BLT_BR30_PAT_ADDRESS_HI(x) ((x) << 0) /* 15:0 */
40+
41 static inline void xy_setup_blt(struct intel_batch * batch,
42 bool monochrome_source_transparency,
43 uint8_t raster_operation,
44@@ -152,19 +164,19 @@ static inline void xy_setup_blt(struct intel_batch * batch,
45 {
46 uint32_t tiling_mode, swizzle_mode;
47
48- intel_batch_ensure_space(batch, 8);
49+ intel_batch_ensure_space(batch, GEN(batch, 8) ? 10 : 8);
50
51 drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
52 drm_intel_bo_emit_reloc_fence
53 (batch->bo, intel_batch_offset(batch, 4), dst, 0,
54 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
55
56- intel_batch_add_dwords(batch, 8,
57+ intel_batch_add_dwords(batch, 4,
58 BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
59 | BLT_BR00_OP(BLT_OP_XY_SETUP_BLT)
60 | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
61 | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
62- | BLT_BR00_DWORD_LENGTH(6),
63+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 8 : 6),
64
65 BLT_BR01_CLIPPING_ENABLE(false)
66 | BLT_BR01_MONO_SRC_TRANSPARENCY(monochrome_source_transparency)
67@@ -178,12 +190,24 @@ static inline void xy_setup_blt(struct intel_batch * batch,
68 | BLT_BR24_CLP_X1(0),
69
70 BLT_BR25_CLP_Y2(0)
71- | BLT_BR25_CLP_X2(0),
72+ | BLT_BR25_CLP_X2(0)
73+ );
74+
75+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
76+ BLT_BR09_DST_ADDRESS(dst->offset64),
77+ /* if gen8 */
78+ BLT_BR27_DST_ADDRESS_HI(dst->offset64 >> 32)
79+ );
80
81- BLT_BR09_DST_ADDRESS(dst->offset),
82+ intel_batch_add_dwords(batch, 2,
83 BLT_BR05_BACKGROUND_COLOR(background_color),
84- BLT_BR06_FOREGROUND_COLOR(foreground_color),
85- BLT_BR07_PAT_ADDRESS(0)
86+ BLT_BR06_FOREGROUND_COLOR(foreground_color)
87+ );
88+
89+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
90+ BLT_BR07_PAT_ADDRESS(0),
91+ /* if gen8 */
92+ BLT_BR30_PAT_ADDRESS_HI(0)
93 );
94 }
95
96@@ -195,7 +219,7 @@ static inline int xy_text_blt(struct intel_batch * batch,
97 {
98 uint32_t tiling_mode, swizzle_mode;
99
100- if (!intel_batch_check_space(batch, 4))
101+ if (!intel_batch_check_space(batch, GEN(batch, 8) ? 5 : 4))
102 return INTEL_BATCH_NO_SPACE;
103
104 drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
105@@ -204,16 +228,21 @@ static inline int xy_text_blt(struct intel_batch * batch,
106 (batch->bo, intel_batch_offset(batch, 3), src, src_offset,
107 I915_GEM_DOMAIN_RENDER, 0);
108
109- intel_batch_add_dwords(batch, 4,
110+ intel_batch_add_dwords(batch, 3,
111 BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
112 | BLT_BR00_OP(BLT_OP_XY_TEXT_BLT)
113 | BLT_BR00_PACKING(BLT_PACKING_BYTE)
114 | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
115- | BLT_BR00_DWORD_LENGTH(2),
116+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 3 : 2),
117
118 BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
119- BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2),
120- BLT_BR12_SRC_ADDRESS(src->offset + src_offset)
121+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2)
122+ );
123+
124+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
125+ BLT_BR12_SRC_ADDRESS(src->offset64 + src_offset),
126+ /* if gen8 */
127+ BLT_BR28_SRC_ADDRESS_HI((src->offset64 + src_offset) >> 32)
128 );
129
130 return INTEL_BATCH_SUCCESS;
131@@ -268,7 +297,7 @@ static inline void xy_src_copy_blt(struct intel_batch * batch,
132 {
133 uint32_t src_tiling_mode, dst_tiling_mode, swizzle;
134
135- intel_batch_ensure_space(batch, 8);
136+ intel_batch_ensure_space(batch, GEN(batch, 8) ? 10 : 8);
137
138 drm_intel_bo_get_tiling(dst, &dst_tiling_mode, &swizzle);
139 drm_intel_bo_get_tiling(src, &src_tiling_mode, &swizzle);
140@@ -277,16 +306,16 @@ static inline void xy_src_copy_blt(struct intel_batch * batch,
141 (batch->bo, intel_batch_offset(batch, 4), dst, 0,
142 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
143 drm_intel_bo_emit_reloc_fence
144- (batch->bo, intel_batch_offset(batch, 7), src, 0,
145+ (batch->bo, intel_batch_offset(batch, GEN(batch, 8) ? 8 : 7), src, 0,
146 I915_GEM_DOMAIN_RENDER, 0);
147
148- intel_batch_add_dwords(batch, 8,
149+ intel_batch_add_dwords(batch, 4,
150 BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
151 | BLT_BR00_OP(BLT_OP_XY_SRC_COPY_BLT)
152 | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
153 | BLT_BR00_SRC_TILING_ENABLE(src_tiling_mode != I915_TILING_NONE)
154 | BLT_BR00_DST_TILING_ENABLE(dst_tiling_mode != I915_TILING_NONE)
155- | BLT_BR00_DWORD_LENGTH(6),
156+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 8 : 6),
157
158 BLT_BR13_CLIPPING_ENABLE(false)
159 | BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
160@@ -297,13 +326,20 @@ static inline void xy_src_copy_blt(struct intel_batch * batch,
161 BLT_BR22_DST_Y1(dst_y) | BLT_BR22_DST_X1(dst_x),
162
163 BLT_BR23_DST_Y2(dst_y + height)
164- | BLT_BR23_DST_X2(dst_x + width),
165-
166- BLT_BR09_DST_ADDRESS(dst->offset),
167+ | BLT_BR23_DST_X2(dst_x + width)
168+ );
169+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
170+ BLT_BR09_DST_ADDRESS(dst->offset64),
171+ BLT_BR27_DST_ADDRESS_HI(dst->offset64 >> 32)
172+ );
173+ intel_batch_add_dwords(batch, 2,
174 BLT_BR26_SRC_Y1(src_y) | BLT_BR26_SRC_X1(src_x),
175 BLT_BR11_SRC_PITCH(src_tiling_mode == I915_TILING_NONE
176- ? src_pitch : src_pitch >> 2),
177- BLT_BR12_SRC_ADDRESS(src->offset)
178+ ? src_pitch : src_pitch >> 2)
179+ );
180+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
181+ BLT_BR12_SRC_ADDRESS(src->offset64),
182+ BLT_BR28_SRC_ADDRESS_HI(src->offset64 >> 32)
183 );
184 }
185
186@@ -315,7 +351,7 @@ static inline void xy_color_blt(struct intel_batch * batch,
187 {
188 uint32_t tiling_mode, swizzle_mode;
189
190- intel_batch_ensure_space(batch, 6);
191+ intel_batch_ensure_space(batch, GEN(batch, 8) ? 7 : 6);
192
193 drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
194
195@@ -323,12 +359,12 @@ static inline void xy_color_blt(struct intel_batch * batch,
196 (batch->bo, intel_batch_offset(batch, 4), dst, 0,
197 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
198
199- intel_batch_add_dwords(batch, 6,
200+ intel_batch_add_dwords(batch, 4,
201 BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
202 | BLT_BR00_OP(BLT_OP_XY_COLOR_BLT)
203 | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
204 | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
205- | BLT_BR00_DWORD_LENGTH(4),
206+ | BLT_BR00_DWORD_LENGTH(GEN(batch, 8) ? 5 : 4),
207
208 BLT_BR13_CLIPPING_ENABLE(false)
209 | BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
210@@ -337,8 +373,13 @@ static inline void xy_color_blt(struct intel_batch * batch,
211 ? dst_pitch : dst_pitch >> 2),
212
213 BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
214- BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2),
215- BLT_BR09_DST_ADDRESS(dst->offset),
216+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2)
217+ );
218+ intel_batch_add_dwords(batch, GEN(batch, 8) ? 2 : 1,
219+ BLT_BR09_DST_ADDRESS(dst->offset64),
220+ BLT_BR27_DST_ADDRESS_HI(dst->offset64 >> 32)
221+ );
222+ intel_batch_add_dword(batch,
223 BLT_BR16_COLOR(color)
224 );
225 }