commit 3f29f42
Michael Forney
·
2014-01-31 22:22:43 +0000 UTC
parent 2b0441a
intel/blt: Drop INTEL_ prefix
2 files changed,
+143,
-146
M
intel.c
M
intel.c
+2,
-2
1@@ -273,7 +273,7 @@ void renderer_draw_text(struct wld_renderer * base,
2 uint8_t * byte;
3 int32_t origin_x = x;
4
5- xy_setup_blt(renderer->batch, true, INTEL_BLT_RASTER_OPERATION_SRC,
6+ xy_setup_blt(renderer->batch, true, BLT_RASTER_OPERATION_SRC,
7 0, color, renderer->target->bo, renderer->target->base.pitch);
8
9 while ((ret = FcUtf8ToUcs4((FcChar8 *) text, &c, length)) > 0 && c != '\0')
10@@ -312,7 +312,7 @@ void renderer_draw_text(struct wld_renderer * base,
11 {
12 intel_batch_flush(renderer->batch);
13 xy_setup_blt(renderer->batch, true,
14- INTEL_BLT_RASTER_OPERATION_SRC, 0, color,
15+ BLT_RASTER_OPERATION_SRC, 0, color,
16 renderer->target->bo, renderer->target->base.pitch);
17 goto retry;
18 }
+141,
-144
1@@ -29,119 +29,119 @@
2
3 #define INTEL_CLIENT_BLT 0x2
4
5-enum intel_blt_op
6+enum blt_op
7 {
8- INTEL_BLT_OP_XY_SETUP_BLT = 0x01,
9- INTEL_BLT_OP_XY_TEXT_BLT = 0x26,
10- INTEL_BLT_OP_XY_TEXT_IMMEDIATE_BLT = 0x31,
11- INTEL_BLT_OP_XY_COLOR_BLT = 0x50,
12- INTEL_BLT_OP_XY_SRC_COPY_BLT = 0x53
13+ BLT_OP_XY_SETUP_BLT = 0x01,
14+ BLT_OP_XY_TEXT_BLT = 0x26,
15+ BLT_OP_XY_TEXT_IMMEDIATE_BLT = 0x31,
16+ BLT_OP_XY_COLOR_BLT = 0x50,
17+ BLT_OP_XY_SRC_COPY_BLT = 0x53
18 };
19
20-enum intel_blt_32bpp_mask
21+enum blt_32bpp_mask
22 {
23- INTEL_BLT_32BPP_MASK_ALPHA = (1 << 0),
24- INTEL_BLT_32BPP_MASK_RGB = (1 << 1)
25+ BLT_32BPP_MASK_ALPHA = (1 << 0),
26+ BLT_32BPP_MASK_RGB = (1 << 1)
27 };
28
29-enum intel_blt_packing
30+enum blt_packing
31 {
32- INTEL_BLT_PACKING_BIT = 0,
33- INTEL_BLT_PACKING_BYTE = 1
34+ BLT_PACKING_BIT = 0,
35+ BLT_PACKING_BYTE = 1
36 };
37
38-enum intel_blt_color_depth
39+enum blt_color_depth
40 {
41- INTEL_BLT_COLOR_DEPTH_8BIT = 0x0,
42- INTEL_BLT_COLOR_DEPTH_16BIT_565 = 0x1,
43- INTEL_BLT_COLOR_DEPTH_16BIT_1555 = 0x2,
44- INTEL_BLT_COLOR_DEPTH_32BIT = 0x3
45+ BLT_COLOR_DEPTH_8BIT = 0x0,
46+ BLT_COLOR_DEPTH_16BIT_565 = 0x1,
47+ BLT_COLOR_DEPTH_16BIT_1555 = 0x2,
48+ BLT_COLOR_DEPTH_32BIT = 0x3
49 };
50
51-enum intel_blt_raster_operation
52+enum blt_raster_operation
53 {
54- INTEL_BLT_RASTER_OPERATION_SRC = 0xcc,
55- INTEL_BLT_RASTER_OPERATION_PAT = 0xf0
56+ BLT_RASTER_OPERATION_SRC = 0xcc,
57+ BLT_RASTER_OPERATION_PAT = 0xf0
58 };
59
60 /* BR00 : BLT Opcode & Control */
61-#define INTEL_BLT_BR00_CLIENT(x) ((x) << 29) /* 31:29 */
62-#define INTEL_BLT_BR00_OP(x) ((x) << 22) /* 28:22 */
63-#define INTEL_BLT_BR00_32BPP_MASK(x) ((x) << 20) /* 21:20 */
64- /* 19:17 */
65-#define INTEL_BLT_BR00_PACKING(x) ((x) << 16) /* 16 */
66-#define INTEL_BLT_BR00_SRC_TILING_ENABLE(x) ((x) << 15) /* 15 */
67- /* 14:12 */
68-#define INTEL_BLT_BR00_DST_TILING_ENABLE(x) ((x) << 11) /* 11 */
69-#define INTEL_BLT_BR00_DWORD_LENGTH(x) ((x) << 0) /* 7:0 */
70+#define BLT_BR00_CLIENT(x) ((x) << 29) /* 31:29 */
71+#define BLT_BR00_OP(x) ((x) << 22) /* 28:22 */
72+#define BLT_BR00_32BPP_MASK(x) ((x) << 20) /* 21:20 */
73+ /* 19:17 */
74+#define BLT_BR00_PACKING(x) ((x) << 16) /* 16 */
75+#define BLT_BR00_SRC_TILING_ENABLE(x) ((x) << 15) /* 15 */
76+ /* 14:12 */
77+#define BLT_BR00_DST_TILING_ENABLE(x) ((x) << 11) /* 11 */
78+#define BLT_BR00_DWORD_LENGTH(x) ((x) << 0) /* 7:0 */
79
80 /* BR01 : Setup BLT Raster OP, Control, and Destination Offset */
81-#define INTEL_BLT_BR01_SOLID_PATTERN(x) ((x) << 31) /* 31 */
82-#define INTEL_BLT_BR01_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
83-#define INTEL_BLT_BR01_MONO_SRC_TRANSPARENCY(x) ((x) << 29) /* 29 */
84-#define INTEL_BLT_BR01_MONO_PAT_TRANSPARENCY(x) ((x) << 28) /* 28 */
85-#define INTEL_BLT_BR01_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
86-#define INTEL_BLT_BR01_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
87-#define INTEL_BLT_BR01_DST_PITCH(x) ((x) << 0) /* 15:0 */
88+#define BLT_BR01_SOLID_PATTERN(x) ((x) << 31) /* 31 */
89+#define BLT_BR01_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
90+#define BLT_BR01_MONO_SRC_TRANSPARENCY(x) ((x) << 29) /* 29 */
91+#define BLT_BR01_MONO_PAT_TRANSPARENCY(x) ((x) << 28) /* 28 */
92+#define BLT_BR01_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
93+#define BLT_BR01_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
94+#define BLT_BR01_DST_PITCH(x) ((x) << 0) /* 15:0 */
95
96 /* BR05 : Setup Expansion Background Color */
97-#define INTEL_BLT_BR05_BACKGROUND_COLOR(x) ((x) << 0) /* 31:0 */
98+#define BLT_BR05_BACKGROUND_COLOR(x) ((x) << 0) /* 31:0 */
99
100 /* BR06 : Setup Expansion Foreground Color */
101-#define INTEL_BLT_BR06_FOREGROUND_COLOR(x) ((x) << 0) /* 31:0 */
102+#define BLT_BR06_FOREGROUND_COLOR(x) ((x) << 0) /* 31:0 */
103
104 /* BR07 : Setup Blit Color Pattern Address */
105- /* 31:29 */
106-#define INTEL_BLT_BR07_PAT_ADDRESS(x) ((x) << 6) /* 28:6 */
107- /* 5:0 */
108+ /* 31:29 */
109+#define BLT_BR07_PAT_ADDRESS(x) ((x) << 6) /* 28:6 */
110+ /* 5:0 */
111
112 /* BR09 : Destination Address */
113- /* 31:29 */
114-#define INTEL_BLT_BR09_DST_ADDRESS(x) ((x) << 0) /* 28:0 */
115+ /* 31:29 */
116+#define BLT_BR09_DST_ADDRESS(x) ((x) << 0) /* 28:0 */
117
118 /* BR11 : Source Pitch */
119- /* 31:16 */
120-#define INTEL_BLT_BR11_SRC_PITCH(x) ((x) << 0) /* 15:0 */
121+ /* 31:16 */
122+#define BLT_BR11_SRC_PITCH(x) ((x) << 0) /* 15:0 */
123
124 /* BR12 : Source Address */
125- /* 31:29 */
126-#define INTEL_BLT_BR12_SRC_ADDRESS(x) ((x) << 0) /* 28:0 */
127+ /* 31:29 */
128+#define BLT_BR12_SRC_ADDRESS(x) ((x) << 0) /* 28:0 */
129
130 /* BR13 : BLT Raster OP, Control, and Destination Pitch */
131-#define INTEL_BLT_BR13_SOLID_PATTERN(x) ((x) << 31) /* 31 */
132-#define INTEL_BLT_BR13_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
133-#define INTEL_BLT_BR13_MONO_SRC_TRANSPARENT(x) ((x) << 29) /* 29 */
134-#define INTEL_BLT_BR13_MONO_PAT_TRANSPARENT(x) ((x) << 28) /* 28 */
135-#define INTEL_BLT_BR13_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
136-#define INTEL_BLT_BR13_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
137-#define INTEL_BLT_BR13_DST_PITCH(x) ((x) << 0) /* 15:0 */
138+#define BLT_BR13_SOLID_PATTERN(x) ((x) << 31) /* 31 */
139+#define BLT_BR13_CLIPPING_ENABLE(x) ((x) << 30) /* 30 */
140+#define BLT_BR13_MONO_SRC_TRANSPARENT(x) ((x) << 29) /* 29 */
141+#define BLT_BR13_MONO_PAT_TRANSPARENT(x) ((x) << 28) /* 28 */
142+#define BLT_BR13_COLOR_DEPTH(x) ((x) << 24) /* 25:24 */
143+#define BLT_BR13_RASTER_OPERATION(x) ((x) << 16) /* 23:16 */
144+#define BLT_BR13_DST_PITCH(x) ((x) << 0) /* 15:0 */
145
146 /* BR16 : Pattern Expansion Background & Solid Pattern Color */
147-#define INTEL_BLT_BR16_COLOR(x) ((x) << 0) /* 31 : 0 */
148+#define BLT_BR16_COLOR(x) ((x) << 0) /* 31 : 0 */
149
150 /* BR22 : Destination Top Left */
151-#define INTEL_BLT_BR22_DST_Y1(x) ((x) << 16) /* 31:16 */
152-#define INTEL_BLT_BR22_DST_X1(x) ((x) << 0) /* 16:0 */
153+#define BLT_BR22_DST_Y1(x) ((x) << 16) /* 31:16 */
154+#define BLT_BR22_DST_X1(x) ((x) << 0) /* 16:0 */
155
156 /* BR23 : Destination Bottom Right */
157-#define INTEL_BLT_BR23_DST_Y2(x) ((x) << 16) /* 31:16 */
158-#define INTEL_BLT_BR23_DST_X2(x) ((x) << 0) /* 16:0 */
159+#define BLT_BR23_DST_Y2(x) ((x) << 16) /* 31:16 */
160+#define BLT_BR23_DST_X2(x) ((x) << 0) /* 16:0 */
161
162 /* BR24 : Clip Rectangle Top Left */
163- /* 31 */
164-#define INTEL_BLT_BR24_CLP_Y1(x) ((x) << 16) /* 30:16 */
165- /* 15 */
166-#define INTEL_BLT_BR24_CLP_X1(x) ((x) << 0) /* 14:0 */
167+ /* 31 */
168+#define BLT_BR24_CLP_Y1(x) ((x) << 16) /* 30:16 */
169+ /* 15 */
170+#define BLT_BR24_CLP_X1(x) ((x) << 0) /* 14:0 */
171
172 /* BR25 : Clip Rectangle Bottom Right */
173- /* 31 */
174-#define INTEL_BLT_BR25_CLP_Y2(x) ((x) << 16) /* 30:16 */
175- /* 15 */
176-#define INTEL_BLT_BR25_CLP_X2(x) ((x) << 0) /* 14:0 */
177+ /* 31 */
178+#define BLT_BR25_CLP_Y2(x) ((x) << 16) /* 30:16 */
179+ /* 15 */
180+#define BLT_BR25_CLP_X2(x) ((x) << 0) /* 14:0 */
181
182 /* BR26 : Source Top Left */
183-#define INTEL_BLT_BR26_SRC_Y1(x) ((x) << 16) /* 31:16 */
184-#define INTEL_BLT_BR26_SRC_X1(x) ((x) << 0) /* 15:0 */
185+#define BLT_BR26_SRC_Y1(x) ((x) << 16) /* 31:16 */
186+#define BLT_BR26_SRC_X1(x) ((x) << 0) /* 15:0 */
187
188 static inline void xy_setup_blt(struct intel_batch * batch,
189 bool monochrome_source_transparency,
190@@ -160,31 +160,30 @@ static inline void xy_setup_blt(struct intel_batch * batch,
191 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
192
193 intel_batch_add_dwords(batch, 8,
194- INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
195- | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_SETUP_BLT)
196- | INTEL_BLT_BR00_32BPP_MASK(INTEL_BLT_32BPP_MASK_ALPHA
197- | INTEL_BLT_32BPP_MASK_RGB)
198- | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
199- | INTEL_BLT_BR00_DWORD_LENGTH(6),
200-
201- INTEL_BLT_BR01_CLIPPING_ENABLE(false)
202- | INTEL_BLT_BR01_MONO_SRC_TRANSPARENCY(monochrome_source_transparency)
203- | INTEL_BLT_BR01_COLOR_DEPTH(INTEL_BLT_COLOR_DEPTH_32BIT)
204- | INTEL_BLT_BR01_RASTER_OPERATION(raster_operation)
205- | INTEL_BLT_BR01_DST_PITCH(tiling_mode == I915_TILING_NONE
206- ? dst_pitch : dst_pitch >> 2),
207+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
208+ | BLT_BR00_OP(BLT_OP_XY_SETUP_BLT)
209+ | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
210+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
211+ | BLT_BR00_DWORD_LENGTH(6),
212+
213+ BLT_BR01_CLIPPING_ENABLE(false)
214+ | BLT_BR01_MONO_SRC_TRANSPARENCY(monochrome_source_transparency)
215+ | BLT_BR01_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
216+ | BLT_BR01_RASTER_OPERATION(raster_operation)
217+ | BLT_BR01_DST_PITCH(tiling_mode == I915_TILING_NONE
218+ ? dst_pitch : dst_pitch >> 2),
219
220 /* XXX: No clipping yet */
221- INTEL_BLT_BR24_CLP_Y1(0)
222- | INTEL_BLT_BR24_CLP_X1(0),
223+ BLT_BR24_CLP_Y1(0)
224+ | BLT_BR24_CLP_X1(0),
225
226- INTEL_BLT_BR25_CLP_Y2(0)
227- | INTEL_BLT_BR25_CLP_X2(0),
228+ BLT_BR25_CLP_Y2(0)
229+ | BLT_BR25_CLP_X2(0),
230
231- INTEL_BLT_BR09_DST_ADDRESS(dst->offset),
232- INTEL_BLT_BR05_BACKGROUND_COLOR(background_color),
233- INTEL_BLT_BR06_FOREGROUND_COLOR(foreground_color),
234- INTEL_BLT_BR07_PAT_ADDRESS(0)
235+ BLT_BR09_DST_ADDRESS(dst->offset),
236+ BLT_BR05_BACKGROUND_COLOR(background_color),
237+ BLT_BR06_FOREGROUND_COLOR(foreground_color),
238+ BLT_BR07_PAT_ADDRESS(0)
239 );
240 }
241
242@@ -206,15 +205,15 @@ static inline int xy_text_blt(struct intel_batch * batch,
243 I915_GEM_DOMAIN_RENDER, 0);
244
245 intel_batch_add_dwords(batch, 4,
246- INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
247- | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_TEXT_BLT)
248- | INTEL_BLT_BR00_PACKING(INTEL_BLT_PACKING_BYTE)
249- | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
250- | INTEL_BLT_BR00_DWORD_LENGTH(2),
251-
252- INTEL_BLT_BR22_DST_Y1(dst_y1) | INTEL_BLT_BR22_DST_X1(dst_x1),
253- INTEL_BLT_BR23_DST_Y2(dst_y2) | INTEL_BLT_BR23_DST_X2(dst_x2),
254- INTEL_BLT_BR12_SRC_ADDRESS(src->offset + src_offset)
255+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
256+ | BLT_BR00_OP(BLT_OP_XY_TEXT_BLT)
257+ | BLT_BR00_PACKING(BLT_PACKING_BYTE)
258+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
259+ | BLT_BR00_DWORD_LENGTH(2),
260+
261+ BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
262+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2),
263+ BLT_BR12_SRC_ADDRESS(src->offset + src_offset)
264 );
265
266 return INTEL_BATCH_SUCCESS;
267@@ -237,14 +236,14 @@ static inline int xy_text_immediate_blt(struct intel_batch * batch,
268 drm_intel_bo_get_tiling(dst, &tiling_mode, &swizzle_mode);
269
270 intel_batch_add_dwords(batch, 3,
271- INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
272- | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_TEXT_IMMEDIATE_BLT)
273- | INTEL_BLT_BR00_PACKING(INTEL_BLT_PACKING_BYTE)
274- | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
275- | INTEL_BLT_BR00_DWORD_LENGTH(1 + dwords),
276-
277- INTEL_BLT_BR22_DST_Y1(dst_y1) | INTEL_BLT_BR22_DST_X1(dst_x1),
278- INTEL_BLT_BR23_DST_Y2(dst_y2) | INTEL_BLT_BR23_DST_X2(dst_x2)
279+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
280+ | BLT_BR00_OP(BLT_OP_XY_TEXT_IMMEDIATE_BLT)
281+ | BLT_BR00_PACKING(BLT_PACKING_BYTE)
282+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
283+ | BLT_BR00_DWORD_LENGTH(1 + dwords),
284+
285+ BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
286+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2)
287 );
288
289 for (index = 0; index < count; ++index)
290@@ -282,30 +281,29 @@ static inline void xy_src_copy_blt(struct intel_batch * batch,
291 I915_GEM_DOMAIN_RENDER, 0);
292
293 intel_batch_add_dwords(batch, 8,
294- INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
295- | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_SRC_COPY_BLT)
296- | INTEL_BLT_BR00_32BPP_MASK(INTEL_BLT_32BPP_MASK_ALPHA
297- | INTEL_BLT_32BPP_MASK_RGB)
298- | INTEL_BLT_BR00_SRC_TILING_ENABLE(src_tiling_mode != I915_TILING_NONE)
299- | INTEL_BLT_BR00_DST_TILING_ENABLE(dst_tiling_mode != I915_TILING_NONE)
300- | INTEL_BLT_BR00_DWORD_LENGTH(6),
301-
302- INTEL_BLT_BR13_CLIPPING_ENABLE(false)
303- | INTEL_BLT_BR13_COLOR_DEPTH(INTEL_BLT_COLOR_DEPTH_32BIT)
304- | INTEL_BLT_BR13_RASTER_OPERATION(INTEL_BLT_RASTER_OPERATION_SRC)
305- | INTEL_BLT_BR13_DST_PITCH(dst_tiling_mode == I915_TILING_NONE
306+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
307+ | BLT_BR00_OP(BLT_OP_XY_SRC_COPY_BLT)
308+ | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
309+ | BLT_BR00_SRC_TILING_ENABLE(src_tiling_mode != I915_TILING_NONE)
310+ | BLT_BR00_DST_TILING_ENABLE(dst_tiling_mode != I915_TILING_NONE)
311+ | BLT_BR00_DWORD_LENGTH(6),
312+
313+ BLT_BR13_CLIPPING_ENABLE(false)
314+ | BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
315+ | BLT_BR13_RASTER_OPERATION(BLT_RASTER_OPERATION_SRC)
316+ | BLT_BR13_DST_PITCH(dst_tiling_mode == I915_TILING_NONE
317 ? dst_pitch : dst_pitch >> 2),
318
319- INTEL_BLT_BR22_DST_Y1(dst_y) | INTEL_BLT_BR22_DST_X1(dst_x),
320+ BLT_BR22_DST_Y1(dst_y) | BLT_BR22_DST_X1(dst_x),
321
322- INTEL_BLT_BR23_DST_Y2(dst_y + height)
323- | INTEL_BLT_BR23_DST_X2(dst_x + width),
324+ BLT_BR23_DST_Y2(dst_y + height)
325+ | BLT_BR23_DST_X2(dst_x + width),
326
327- INTEL_BLT_BR09_DST_ADDRESS(dst->offset),
328- INTEL_BLT_BR26_SRC_Y1(src_y) | INTEL_BLT_BR26_SRC_X1(src_x),
329- INTEL_BLT_BR11_SRC_PITCH(src_tiling_mode == I915_TILING_NONE
330- ? src_pitch : src_pitch >> 2),
331- INTEL_BLT_BR12_SRC_ADDRESS(src->offset)
332+ BLT_BR09_DST_ADDRESS(dst->offset),
333+ BLT_BR26_SRC_Y1(src_y) | BLT_BR26_SRC_X1(src_x),
334+ BLT_BR11_SRC_PITCH(src_tiling_mode == I915_TILING_NONE
335+ ? src_pitch : src_pitch >> 2),
336+ BLT_BR12_SRC_ADDRESS(src->offset)
337 );
338 }
339
340@@ -326,23 +324,22 @@ static inline void xy_color_blt(struct intel_batch * batch,
341 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
342
343 intel_batch_add_dwords(batch, 6,
344- INTEL_BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
345- | INTEL_BLT_BR00_OP(INTEL_BLT_OP_XY_COLOR_BLT)
346- | INTEL_BLT_BR00_32BPP_MASK(INTEL_BLT_32BPP_MASK_ALPHA
347- | INTEL_BLT_32BPP_MASK_RGB)
348- | INTEL_BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
349- | INTEL_BLT_BR00_DWORD_LENGTH(4),
350-
351- INTEL_BLT_BR13_CLIPPING_ENABLE(false)
352- | INTEL_BLT_BR13_COLOR_DEPTH(INTEL_BLT_COLOR_DEPTH_32BIT)
353- | INTEL_BLT_BR13_RASTER_OPERATION(INTEL_BLT_RASTER_OPERATION_PAT)
354- | INTEL_BLT_BR13_DST_PITCH(tiling_mode == I915_TILING_NONE
355- ? dst_pitch : dst_pitch >> 2),
356-
357- INTEL_BLT_BR22_DST_Y1(dst_y1) | INTEL_BLT_BR22_DST_X1(dst_x1),
358- INTEL_BLT_BR23_DST_Y2(dst_y2) | INTEL_BLT_BR23_DST_X2(dst_x2),
359- INTEL_BLT_BR09_DST_ADDRESS(dst->offset),
360- INTEL_BLT_BR16_COLOR(color)
361+ BLT_BR00_CLIENT(INTEL_CLIENT_BLT)
362+ | BLT_BR00_OP(BLT_OP_XY_COLOR_BLT)
363+ | BLT_BR00_32BPP_MASK(BLT_32BPP_MASK_ALPHA | BLT_32BPP_MASK_RGB)
364+ | BLT_BR00_DST_TILING_ENABLE(tiling_mode != I915_TILING_NONE)
365+ | BLT_BR00_DWORD_LENGTH(4),
366+
367+ BLT_BR13_CLIPPING_ENABLE(false)
368+ | BLT_BR13_COLOR_DEPTH(BLT_COLOR_DEPTH_32BIT)
369+ | BLT_BR13_RASTER_OPERATION(BLT_RASTER_OPERATION_PAT)
370+ | BLT_BR13_DST_PITCH(tiling_mode == I915_TILING_NONE
371+ ? dst_pitch : dst_pitch >> 2),
372+
373+ BLT_BR22_DST_Y1(dst_y1) | BLT_BR22_DST_X1(dst_x1),
374+ BLT_BR23_DST_Y2(dst_y2) | BLT_BR23_DST_X2(dst_x2),
375+ BLT_BR09_DST_ADDRESS(dst->offset),
376+ BLT_BR16_COLOR(color)
377 );
378 }
379